PIC18F458-E/P Microchip Technology, PIC18F458-E/P Datasheet - Page 99

IC MCU FLASH 16KX16 W/CAN 40 DIP

PIC18F458-E/P

Manufacturer Part Number
PIC18F458-E/P
Description
IC MCU FLASH 16KX16 W/CAN 40 DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F458-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F458-E/P
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F458-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
FIGURE 9-4:
© 2006 Microchip Technology Inc.
Note 1: I/O pins have diode protection to V
RBPU
Data Bus
WR LATB
or
WR PORTB
WR TRISB
RD TRISB
RD LATB
RBx/INTx
RD PORTB
Set RBIF
From other
RB7:RB4 pins
2: To enable weak pull-ups, set the appropriate TRIS
(2)
bit(s) and clear the RBPU bit (INTCON2 register).
Data Latch
TRIS Latch
D
D
CK
CK
RB7:RB4 PINS BLOCK
DIAGRAM
Q
Q
Q
Q
Latch
EN
EN
D
TTL
Input
Buffer
D
DD
and V
V
P
DD
Weak
Pull-up
I/O pin
SS
Buffer
.
Q1
Q3
ST
(1)
FIGURE 9-5:
Note 1: I/O pins have diode protection to V
RBPU
Data Bus
WR TRIS
RD TRIS
RD Port
RBx/INTx
WR Port
2: To enable weak pull-ups, set the appropriate TRIS
(2)
bit(s) and clear the RBPU bit (INTCON2 register).
TRIS Latch
Data Latch
D
D
CK
CK
RB1:RB0 PINS BLOCK
DIAGRAM
Q
Q
PIC18FXX8
Q
Schmitt Trigger
Buffer
EN
DS41159E-page 97
D
DD
TTL
Input
Buffer
and V
V
P
DD
SS
Weak
Pull-up
I/O pin
.
(1)

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