PIC18F458-E/P Microchip Technology, PIC18F458-E/P Datasheet - Page 75

• Manufacturer Part Number: PIC18F458-E/P
• Description: IC MCU FLASH 16KX16 W/CAN 40 DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset or a WDT
Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
© 2006 Microchip Technology Inc.
WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
Required
Sequence
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
MOVFW
MOVWF
TBLWT+*
DECFSZ COUNTER
BRA
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ COUNTER_HI
BRA
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
POSTINC0, W
TABLAT
WRITE_WORD_TO_HREGS
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
PROGRAM_LOOP
EECON1, WREN
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
6.5.4
To reduce the probability against spurious writes to
Flash program memory, the write initiate sequence
must also be followed. See Section 24.0 “Special
Features of the CPU” for more detail.
6.6
See Section 24.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
Flash Program Operation During
Code Protection
PROTECTION AGAINST SPURIOUS
WRITES
PIC18FXX8
DS41159E-page 73