PIC18F458-E/P Microchip Technology, PIC18F458-E/P Datasheet - Page 235

• Manufacturer Part Number: PIC18F458-E/P
• Description: IC MCU FLASH 16KX16 W/CAN 40 DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.7
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitters clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18FXX8 is implemented using
a DPLL that is configured to synchronize to the
incoming data and provides the nominal timing for the
transmitted data. The DPLL breaks each bit time into
multiple segments made up of minimal periods of time
called the Time Quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of time quanta in each segment.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
FIGURE 19-7:
© 2006 Microchip Technology Inc.
Input
Signal
Bit
Time
Intervals
T
Q
Baud Rate Setting
Segment
BIT TIME PARTITIONING
Sync
Q
).
Propagation
Segment
Nominal Bit Time
Segment 1
Phase
The Nominal Bit Time is defined as:
The nominal bit time can be thought of as being divided
into separate, non-overlapping time segments. These
segments (Figure 19-7) include:
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus, the nominal bit time) are,
in turn, made up of integer units of time called time
quanta or T
nominal bit time is programmable from a minimum of
8 T
minimum nominal bit time is 1 s corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the relationship:
The time quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is
where F
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1<5:0>.
Q
Nominal Bit Time = T
to a maximum of 25 T
Sample Point
OSC
T
T
Q
Q
( s) = (2 * (BRP + 1))/F
( s) = (2 * (BRP + 1)) * T
Q
Phase_Seg1 + Phase_Seg2)
is the clock frequency, T
T
(see Figure 19-7). By definition, the
BIT
= 1/Nominal Bit Rate
Q
PIC18FXX8
* (Sync_Seg + Prop_Seg +
or
Segment 2
Q
Phase
. Also, by definition, the
OSC
DS41159E-page 233
OSC
(MHz)
( s)
OSC
is the