PIC18F458-E/P Microchip Technology, PIC18F458-E/P Datasheet - Page 27

• Manufacturer Part Number: PIC18F458-E/P
• Description: IC MCU FLASH 16KX16 W/CAN 40 DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
The PIC18FXX8 differentiates between various kinds
of RESET:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
FIGURE 3-1:
© 2006 Microchip Technology Inc.
MCLR
OSC1
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset during normal
operation
Programmable Brown-out Reset (PBOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
DD
Instruction
RESET
RESET
Pointer
RC OSC
Stack
2: See Table 3-1 for time-out situations.
On-chip
OST/PWRT
Brown-out
V
Module
Detect
DD
WDT
Reset
(1)
Rise
Stack Full/Underflow Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Time-out
Reset
WDT
10-bit Ripple Counter
External Reset
10-bit Ripple Counter
BOREN
Power-on Reset
Sleep
state on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
A WDT Reset does not drive MCLR pin low.
PIC18FXX8
S
R
Enable PWRT
Enable OST
DS41159E-page 25
Q
Chip_Reset
(2)