ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 129
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ATTINY88-15MZ
Manufacturer Part Number
ATTINY88-15MZ
Description
IC MCU AVR 8B 8KB FLASH 32QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY88-15MZ.pdf
(246 pages)
Specifications of ATTINY88-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY88-15MZ
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATTINY88-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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15.2.2
15.3
15.3.1
15.3.2
9157B–AVR–01/10
Data Transfer and Frame Format
Electrical Interconnection
Transferring Bits
START and STOP Conditions
The PRTWI bit in
enable the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 15-2. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted.
SDA
SCL
Figure
“PRR – Power Reduction Register” on page 38
15-1, both bus lines are connected to the positive supply voltage through
Data Stable
“2-wire Serial Interface Characteristics” on page
Data Change
Data Stable
ATtiny88 Automotive
must be written to zero to
213. Two
129
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