ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 113

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.11.6
12.11.7
12.11.8
9157B–AVR–01/10
OCR1BH and OCR1BL – Output Compare Register 1 B
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter1 Interrupt Mask Register
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7, 6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 48) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 88.
See “Accessing 16-bit Registers” on page 88.
R/W
R/W
R
7
–
0
7
0
7
0
R/W
R/W
R
6
0
6
0
6
–
0
ICIE1
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R
4
–
0
4
0
4
0
OCR1B[15:8]
OCR1B[7:0]
ICR1[15:8]
ICR1[7:0]
R/W
R/W
R
3
–
0
3
0
3
0
ATtiny88 Automotive
OCIE1B
R/W
R/W
R/W
2
0
2
0
2
0
OCIE1A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE1
R/W
R/W
R/W
0
0
0
0
0
0
OCR1BH
OCR1BL
TIMSK1
ICR1H
ICR1L
113