ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 61

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
Caution:
Table 29.
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
reading the DR register will read the alternate function output status.
the alternate function reads the pin status given by the DR register content.
Not implemented in
true open drain
I/O ports
Not implemented in
true open drain
I/O ports
Not implemented in
true open drain
I/O ports
I/O port configurations
Pad
Pad
Pad
V
V
R
R
DD
DD
PU
PU
V
R
DD
PU
Hardware configuration
Pull-up
condition
condition
Interrupt
Alternate
Alternate
enable
enable
register
DR
External interrupt
source (ei
register
register
DR register access
DR
DR
DR register access
DR register access
W
R
Alternate
Alternate
x
)
output
output
R/W
R/W
Analog input
Alternate input
Data bus
Data bus
Data bus
I/O ports
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