ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 188
ST72F324BJ6B6
Manufacturer Part Number
ST72F324BJ6B6
Description
MCU 8BIT 32KB FLASH/ROM 42-SDIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F324BJ6B6.pdf
(193 pages)
Specifications of ST72F324BJ6B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SDIP (0.600", 15.24mm)
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
No. Of Pwm Channels
3
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5589-5
- Current page: 188 of 193
- Download datasheet (3Mb)
Known limitations
15.1.5
15.1.6
15.1.7
188/193
Nested interrupt context
The symptom does not occur when the interrupts are handled normally, that is, when:
●
●
●
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs then output
compare flag gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If output compare interrupt is enabled, then the output compare flag cannot be cleared in the
timer interrupt routine. Consequently the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer then the timer interrupts.
●
●
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
●
●
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine with higher or identical priority
level
The interrupt flag is cleared in any part of the code while this interrupt is disabled
–
–
–
–
Perform the following to disable the timer:
–
–
Perform the following to enable the timer again:
–
–
20 bits instead of 10 bits if M = 0
22 bits instead of 11 bits if M = 1
PUSH CC
SIM
Reset interrupt flag
POP CC
TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR I or TBCSR I = 0x40; // Disable the timer
TACSR & or TBCSR & = ~0x40; // Enable the timer
TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
ST72324Bxx
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