ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 49

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
7.6.2
External interrupt control register (EICR)
Table 19.
Table 20.
EICR
7:6 IS1[1:0]
4:3 IS2[1:0]
1:0
Bit
5
2
IS11
IS11
R/W
0
0
1
1
7
Name
IPB
IPA
-
EICR register description
Interrupt sensitivity - ei2
IS10
ei2 and ei3 sensitivity
Interrupt Polarity (for port B)
ei0 and ei1 sensitivity
Interrupt Polarity (for port A)
Reserved, must always be kept cleared
0
1
0
1
IS10
R/W
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 for port B [3:0] (see
- ei3 for port B4 (see
Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
- ei0 for port A[3:0] (see
- ei1 for port F[2:0] (see
Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion.
1: Sensitivity inversion.
6
Falling edge and low level
R/W
IPB
5
Falling edge only
Rising edge only
IPB bit = 0
Table
IS21
R/W
Table
Table
Table
4
21)
External interrupt sensitivity
23)
22)
20)
Rising and falling edge
Function
IS20
R/W
3
R/W
IPA
Rising edge and high level
2
Reset value: 0000 0000 (00h)
Falling edge only
Rising edge only
IPB bit = 1
1
Reserved
-
Interrupts
0
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