PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 20

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F872X FAMILY
3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADRH:EEADR) and
a data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA with the data to be written and
initiating a memory write by appropriately configuring
the EECON1 register (Register 3-1). A byte write auto-
matically erases the location and writes the new data
(erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC must
still be held low for the time specified by parameter, P10,
to allow high-voltage discharge of the memory array.
FIGURE 3-8:
DS39643C-page 20
PGD
PGC
Poll WR bit
Data EEPROM Programming
4-Bit Command
1 2
0 0 0 0
3
PGC
PGD
4
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
4-Bit Command
2
1 2
0 0 0 0
15 16
3
4
P5A
P5
MOVF EECON1, W, 0
1
2
PGD = Input
PGD = Input
15 16
P5A
4-Bit Command
1
0 0 0 0
Poll WR Bit, Repeat until Clear
FIGURE 3-7:
2
3
P11A
(see below)
4
P5
MOVWF TABLAT
1
No
2
15 16
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
© 2009 Microchip Technology Inc.
Set Data
WR bit
clear?
Done?
Done
Start
P5A
Yes
Yes
(see Figure 4-4)
Shift Out Data
PGD = Output
No
P10
16-Bit Data
Payload
1
n
2
n