MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet
MT46V128M8
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MT46V128M8 Summary of contents
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... MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. MT46V256M4 – 64 MEG BANKS MT46V128M8 – 32 MEG BANKS MT46V64M16 – 16 MEG BANKS For the latest data sheet revisions, please refer to the Micron Web site: www ...
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DDR SDRAM Part Numbers Example Part Number: MT46V64M16TG-75 - MT46V Configuration Package Speed Configuration 256 Meg x4 256M4 128 Meg x8 128M8 64 Meg x16 64M16 Package 400 mil TSOP TG 400 mil TSOP Lead-Free P -75 General Description ...
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TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Pin Assignment (Top View) 66-pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Ball/Pin Descriptions ...
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Figure 2: Functional Block Diagram 256 Meg x4 CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 14 MODE REGISTERS COUNTER 16 14 A0-A13, ADDRESS 16 BA0, BA1 REGISTER 2 12 09005aef8076894f 1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN BANK3 ...
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Figure 3: Functional Block Diagram 128 Meg x8 CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 14 MODE REGISTERS COUNTER 16 14 A0-A13, ADDRESS 16 BA0, BA1 REGISTER 2 11 09005aef8076894f 1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN BANK3 ...
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Figure 4: Functional Block Diagram 64 Meg x16 CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 14 COUNTER MODE REGISTERS 16 14 A0-A13, ADDRESS 16 BA0, BA1 REGISTER 2 10 09005aef8076894f 1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN BANK3 ...
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Table 1: Ball/Pin Descriptions TSOP NUMBERS SYMBOL 45, 46 CK, CK# 44 CKE 24 CS# 23, 22, RAS#, CAS 20, 47 LDM, UDM 26, 27 BA0, BA1 29, 30, 31, 32, A0, A1, A2, A3, 35, ...
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Table 1: Ball/Pin Descriptions (Continued) TSOP NUMBERS SYMBOL DQ0–DQ2 11, 56, 59, DQ3–DQ5 62, 65 DQ6, DQ7 5, 11, 56, DQ0–DQ2 62 DQ3 51 DQS 16 LDQS 51 UDQS 14, 25, NC 43, 53 19, 50 DNU ...
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Functional Description The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random-access memory 1,073,741,824 bits. The 1Gb DDR SDRAM is internally configured as a quad-bank DRAM. The 1Gb DDR SDRAM uses a double data rate archi- tecture to achieve high-speed ...
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Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being program- mable, as shown in Figure 5. The burst length deter- mines the maximum number of column locations that can be accessed ...
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Table 2: Burst Definition ORDER OF ACCESSES WITHIN A STARTING BURST COLUMN TYPE= LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, and out- put drive strength. These functions are controlled via the bits shown in Figure 7. The extended ...
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Commands Table 4 and Table 5 provide a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Table 4: Truth Table – Commands Note 1 applies to all commands NAME (FUNCTION) ...
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DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to ...
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Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time ( completed. BURST TERMINATE The BURST TERMINATE command is used to trun- cate ...
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Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and ...
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READs READ bursts are initiated with a READ command, as shown in Figure 10 on page 20. The starting column and bank addresses are pro- vided with the READ command and auto precharge is either enabled or disabled for that ...
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Rev. A 3/03 EN Figure 10: READ Command CK# CK CKE HIGH CS# RAS# CAS# WE# x4: A0–A9, A11, A12 CA x8: A0–A9, A11 x16: A0–A9 x4: A13 x8: A12, A13 x16: A11, A12, A13 EN AP ...
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T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. Burst length = 4. 3. Three ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ NOTE ( data-out from column n (or column b). 2. Burst ...
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Figure 13: Nonconsecutive READ Bursts T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ NOTE ( data-out from column n ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ NOTE ( data-out from column n (or ...
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Figure 15: Terminating a READ Burst T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ DM NOTE data-out from column data-in from ...
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T0 CK COMMAND READ Bank a, ADDRESS Col n DQS COMMAND READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. Burst length = 4, ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto ...
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CK# CK COMMAND ADDRESS t DQSS (NOM) DQS DQSS (MIN) DQS DQSS (MAX) DQS DQ DM NOTE data-in for column b. 2. Three subsequent elements of data-in are applied in ...
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Figure 20: Consecutive WRITE to WRITE T0 CK# CK COMMAND WRITE Bank, ADDRESS Col DQSS (NOM) DQSS DQS DQ DM NOTE etc. = data-in for column b, etc. 2. Three subsequent elements of data-in ...
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Figure 21: Nonconsecutive WRITE to WRITE T0 CK# CK COMMAND WRITE Bank, ADDRESS Col DQSS (NOM) DQSS DQS DQ DM NOTE etc. = data-in for column b, etc. 2. Three subsequent elements of data-in ...
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T0 CK# CK COMMAND WRITE Bank, ADDRESS Col b t DQSS (NOM) DQS DQ DM NOTE etc. = data-in for column b, etc. 2. b', etc. = the next data-in following DI b, etc., according to the ...
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Figure 23: WRITE to READ - Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS ...
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Figure 24: WRITE to READ - Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 25: WRITE to READ - Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS ...
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Figure 26: WRITE to PRECHARGE - Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 27: WRITE to Precharge – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 28: WRITE to PRECHARGE Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS ...
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PRECHARGE The PRECHARGE command as shown in Figure 29, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be avail- able for a subsequent row access some specified ...
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T0 CK# CK CKE COMMAND VALID No READ/WRITE access in progress Table 6: Truth Table – CKE Notes: 1-6 CKE CKE CURRENT STATE n Power-Down Self Refresh L H Power-Down Self Refresh H L All Banks Idle ...
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Table 7: Truth Table – Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# Any Idle ...
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Write w/Auto- Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when has been met. Once RP is met, the bank will be in the idle state. 5. The following states ...
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Table 8: Truth Table – Current State Bank n - Command to Bank m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# Any Idle Row L L Activating, L ...
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This device supports concurrent auto precharge such that when a read with auto pre- charge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Transmitter 09005aef8076894f 1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN Figure 31: Input Voltage Waveform V Q (2.3V minimum (1.670V for SSTL2 termination) OH(MIN) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V 1.400V 1.300V 1.275V 1.250V 1.225V 1.200V ...
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Table 11: Clock Input Operating Conditions 0°C £ T £ +70° +2.5V ±0.2V Notes: 1–5, 15, 16, 30; notes appear on page 54-57 PARAMETER/CONDITION Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage ...
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Table 12: Capacitance (x4, x8) (Note: 13; notes appear on page 54-57) PARAMETER Delta Input/Output Capacitance: DQ0-DQ3 (x4), DQ0-DQ7 (x8) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and ...
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Table 14: I Specifications and Conditions (x4, x8) DD 0°C £ T £ +70° +2.5V ±0.2V Notes: 1–5, 10, 12, 14; notes appear on page 54-57; See also Table 16, I PARAMETER/CONDITION OPERATING CURRENT: ...
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Table 15: I Specifications and Conditions (x16) DD 0°C £ T £ +70° +2.5V ±0.2V Notes: 1–5, 10, 12, 14; notes appear on page 54-57; See also Table 16, I PARAMETER/CONDITION OPERATING CURRENT: One ...
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Table 16: I Test Cycle Times DD Values reflect number of clock cycles for each test. SPEED CLOCK IDD TEST GRADE CYCLE TIME I 0 -75 7.5ns -75 7.5ns -75 7.5ns ...
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Table 17: Electrical Characteristics and Recommended AC Operating Conditions 0°C £ T £ +70° +2.5V ±0.2V Notes: 1–5, 14–17, 33, notes appear on page 54-57 AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# ...
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Table 18: Input Slew Rate Derating Values for Addresses and Commands 0°C £ T £ +70° +2.5V ±0.2V Notes: 14; notes appear on page 54-57 SPEED SLEW RATE -75 0.500V / ns -75 0.400V ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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RAS (MAX) for I measurements is the DD t largest multiple of CK that meets the maxi- t mum absolute value for RAS. 23. The refresh period is 64ms. This equates ...
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The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount 34. HP (MIN) is the lesser of CL minimum and minimum actually applied to the device CK ...
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The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full ...
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Table 20: Normal Output Drive Characteristics PULL-DOWN CURRENT (mA) VOLTAGE NOMINAL NOMINAL (V) LOW HIGH 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 ...
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Table 21: Reduced Output Drive Characteristics PULL-DOWN CURRENT (mA) VOLTAGE NOMINAL NOMINAL (V) LOW HIGH 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.9 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 ...
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Figure 38: x4, x8 Data Output Timing – CK DQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First ...
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Figure 39: x16 Data Output Timing – CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ0 - DQ7 ...
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Figure 40: Data Output Timing – CK (MIN) 2 DQS, or LDQS/UDQS DQ (Last data valid) DQ (First data valid) 3 All DQ values, collectively NOTE DQSCK is the DQS output window relative ...
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Figure 42: Initialize And Load Mode Registers ( ( ) ) VTD ( ( ) REF ) ) CK ...
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T0 CK CKE VALID 1 COMMAND ADDR VALID DQS DQ DM NOTE this command is a PRECHARGE (or if the device is already in the ...
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CKE NOP 2 COMMAND PRE A0-A9, A11 1 A12, A13 ALL BANKS 1 A10 ONE BANK Bank(s) 4 BA0, BA1 5 ...
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CKE COMMAND NOP AR ADDR DQS Enter Self Refresh Mode NOTE: 1. Clock must ...
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Figure 46: Bank Read - Without Auto Precharge CKE NOP 6 COMMAND ACT t IS x4: A0-A9, A11, A12 x8: A0-A9, A11 RA x16: A0-A9 x4: A13 ...
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Figure 47: Bank Read - With Auto Precharge CKE NOP 5 COMMAND ACT t IS x4: A0-A9, A11, A12 x8: A0-A9, A11 RA x16: A0-A9 x4: A13 ...
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Figure 48: Bank Write - Without Auto Precharge CKE NOP 6 COMMAND ACT t IS x4: A0-A9, A11, A12 x8: A0-A9, A11 RA x16: A0-A9 x4: A13 ...
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Figure 49: Bank Write - With Auto Precharge CKE NOP 5 COMMAND ACT t IS x4: A0-A9, A11, A12 x8: A0-A9, A11 RA x16: A0-A9 x4: A13 ...
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CKE NOP 6 COMMAND ACT t IS x4: A0-A9, A11, A12 x8: A0-A9, A11 RA x16: A0-A9 x4: A13 x8: A21, A13 RA x16: A11, A12, A13 ...
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Figure 51: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP PIN #1 ID NOTE: 1. All dimensions in millimeters 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm ...
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Rev. A 3/03 EN 1Gb: x4, x8, x16 Micron Technology, Inc., reserves the right to change products or specifications without notice. 73 PRELIMINARY DDR SDRAM ©2003 Micron Technology. Inc. ...
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S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks ...