MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 55

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
23. The refresh period is 64ms. This equates to an
24. The I/O capacitance per DQS and DQ byte/group
25. The data valid window is derived by achieving
26. Referenced to each output group: x4 = DQS with
mum absolute value for the respective parame-
ter.
largest multiple of
mum absolute value for
average refresh rate of 7.8125µs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3µs; burst refreshing or post-
ing by the DRAM controller greater than eight
refresh cycles is not allowed.
will not differ by more than this maximum
amount for any given device.
other specifications -
t
derates in direct proportion to the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55, because functionality
is uncertain when operating beyond a 45/55
ratio. The data valid window derating curves are
provided in Figure 33 for duty cycles ranging
between 50/50 and 45/55.
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS
with DQ0-DQ7; and UDQS with DQ8-DQ15.
QH (
t
RAS (MAX) for I
t
QH =
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
HP -
Figure 33: Derating Data Valid Window (
50/50
3.750
2.500
t
QHS). The data valid window
—— -75 @
—— -75 @
t
CK that meets the maxi-
49.5/50.5
DD
t
3.700
HP (
t
2.463
RAS.
measurements is the
t
t
CK = 10ns
CK = 7.5ns
t
CK/2),
3.650
49/51
2.425
t
DQSQ, and
48.5/52.5
3.600
2.388
3.550
48/52
2.350
Cl o ck Du ty C y c le
55
47.5/53.5
3.500
27. This limit is actually a nominal value and does not
28. To maintain a valid level, the transitioning edge of
29. The Input capacitance per pin group will not dif-
30. CK and CK# input slew rate must be ³ 1V/ns
31. DQ and DM input slew rates must not deviate
32. V
2.313
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue
fer by more than this maximum amount for any
given device.
( ³ 2V/ns if measured differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
If slew rate exceeds 4V/ns, functionality is uncer-
tain.
not active while any bank is active.
DH for each 100mv/ns reduction in slew rate. For
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
3.450
47/53
AC level through to the target AC level,
V
to maintain at least the target DC level,
V
2.275
IL
IL
must not vary more than 4 percent if CKE is
(AC) or V
(DC) or V
46.5/54.5
3.400
2.238
t
QH -
IH
IH
(AC).
3.350
46/54
(DC).
2.200
t
DQSQ)
1Gb: x4, x8, x16
45.5/55.5
3.300
2.163
DDR SDRAM
PRELIMINARY
t
RFC [MIN]) else
3.250
45/55
©2003 Micron Technology. Inc.
2.125
t
DS and