MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 14

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable, and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7. The extended mode register
is programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
fied to be SSTL_2, Class II. The x16 supports a pro-
grammable option for reduced drive. This option is
intended for the support of the lighter load and/or
point-to-point environments. The selection of the
reduced drive strength will alter the DQ pins and DQS
pins from SSTL_2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of
the SSTL_2, Class II drive strength.
DLL Enable/Disable
device functionality may be altered. The DLL must be
enabled for normal operation. DLL enable is required
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
The extended mode register controls functions
The extended mode register must be loaded when
The normal drive strength for all outputs are speci-
When the part is running without the DLL enabled,
14
during power-up initialization and upon returning to
normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automati-
cally.) Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
NOTE:
Figure 7: Extended Mode Register
E13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
0
–
15
BA1 BA0
1
1
E12
1. E15 and E14 (BA1 and BA0) must be “0, 1” to
2. The reduced drive strength option is not sup-
3. The QFC# option is not supported.
14
1
0
–
E11
13
select the Extended Mode Register vs. the base
Mode Register.
ported on the x4 and x8 versions, and is only
available on the x16 version.
0
–
A13
E10
12
A12
0
–
11
E9
A11
0
–
10
E8
0
–
A10
Operating Mode
E7
0
–
9
Definition
A9
E6 E5
0
–
8
A8
0
–
7
A7 A6 A5 A4 A3
E4
0
–
1Gb: x4, x8, x16
6
E3
0
–
5
E2
0
–
4
DDR SDRAM
3
E1,
Valid
–
2
E0
A2 A1 A0
PRELIMINARY
DS
1
E1
©2003 Micron Technology. Inc.
0
1
DLL
2
Operating Mode
Reserved
Reserved
0
E0
0
1
Extended Mode
Register (Ex)
Drive Strength
Address Bus
Reduced
Normal
Disable
Enable
DLL