MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 12

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Burst Length
burst oriented, with the burst length being program-
mable, as shown in Figure 5. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two,
by A2-Ai when the burst length is set to four and by A3-
Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given config-
uration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 2, Burst
Definition, on page 13.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
Read and write accesses to the DDR SDRAM are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
12
Figure 5: Mode Register Definition
* M15 and M14 (BA1 and BA0)
0*
BA1
15
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
BA0
14
A13
13
12
A12 A11
Operating Mode
11
M13
0
0
-
10
A10
M12 M11
0
0
-
9
A9
0
0
-
8
A8
M10
0
0
-
7
A7 A6 A5 A4 A3
M9
M6
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
1Gb: x4, x8, x16
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
M6-M0
M3
0
1
Valid
Valid
3
-
DDR SDRAM
Burst Length
M2
2
0
0
0
0
1
1
1
1
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
PRELIMINARY
2
M0
0
1
0
1
0
1
0
1
0
©2003 Micron Technology. Inc.
Burst Type
Interleaved
Sequential
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
2
4
8