MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 34

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DI b = data-in for column b, DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ command would not mask these
t
two data elements.
WTR is referenced from the first positive CK edge after the last data-in pair.
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
Figure 24: WRITE to READ - Interrupting
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
T2n
34
Bank a,
READ
Col n
T3
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DON’T CARE
CL = 2
CL = 2
CL = 2
T4
NOP
TRANSITIONING DATA
T5
NOP
1Gb: x4, x8, x16
DO
DO
DO
n
n
n
T5n
DDR SDRAM
PRELIMINARY
©2003 Micron Technology. Inc.
T6
NOP
T6n