MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet
MPC860DP
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MPC860DP Summary of contents
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Freescale Semiconductor Technical Data MPC860 Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family. 1 Overview The MPC860 Power Quad Integrated Communications Controller (PowerQUICC™ ...
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... Features Cache (Kbytes) Part Instruction Cache MPC860DE 4 MPC860DT 4 MPC860DP 16 MPC860EN 4 MPC860SR 4 MPC860T 4 MPC860P 16 MPC855T 4 1 Supporting documentation for these devices refers to the following: 1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev MPC855T User’s Manual (MPC855TUM/D, Rev Features The following list summarizes the key MPC860 features: • ...
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Each bank can be a chip select or RAS to support a DRAM bank. — wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices — ...
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Features — UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system clock ratios of 1/2 or 1/3. — Serial-mode ATM connection supports transmission convergence (TC) ...
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Multiple-master environment support • Time-slot assigner (TSA) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 8-bit resolution — ...
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Thermal Characteristics (GND = 0 V) Rating 1 Supply voltage 2 Input voltage 3 Temperature (standard) 3 Temperature (extended) Storage temperature range 1 The power supply of the device must start its ramp from 0 Functional operating conditions ...
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Rating Mold Compound Thickness 1 Junction-to-ambient Natural convection Airflow (200 ft/min) 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package top Natural convection 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air ...
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DC Characteristics 6 DC Characteristics Table 6 provides the DC electrical characteristics for the MPC860. Characteristic Operating voltage at 40 MHz or less Operating voltage greater than 40 MHz Input high voltage (all inputs except EXTAL and EXTCLK) 1 Input ...
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A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/ VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/ PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/ PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, ...
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Thermal Calculation and Measurement printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. ...
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Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2 more accurate and complex ...
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Bus Signal Timing All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation ...
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Num Characteristic B7a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR invalid B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), 4 LWP(0:1), STS invalid B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31), DP(0:3) valid B8a CLKOUT to TSIZ(0:1), REG, ...
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Bus Signal Timing Num Characteristic B18 D(0:31), DP(0:3) valid to CLKOUT rising edge (setup time) B19 CLKOUT rising edge to D(0:31), DP(0:3) valid (hold time) B20 D(0:31), DP(0:3) valid to CLKOUT falling edge (setup time) B21 CLKOUT falling edge to ...
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Num Characteristic B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0, 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 B28c CLKOUT falling edge to WE(0:3) negated GPCM write access TRLX ...
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Table 7. Bus Operation Timings (continued) Num Characteristic B29i CS negated to D(0:31), DP(0:3) High-Z GPCM write access, How to Reach Us: TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 Home Page: ...
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Num Characteristic B30 CS, WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write 8 access B30a WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access, TRLX = ...
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Bus Signal Timing Num Characteristic B31d CLKOUT falling edge to CS valid—as requested by control bit CST1 in the corresponding word in UPM, EBDF = 1 B32 CLKOUT falling edge to BS valid—as requested by control bit BST4 in the ...
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Num Characteristic B35 A(0:31), BADDR(28:30 valid—as requested by control bit BST4 in the corresponding word in UPM B35a A(0:31), BADDR(28:30), and D(0:31 valid—as requested by control bit BST1 in the corresponding word in UPM B35b A(0:31), ...
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Bus Signal Timing 8 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. 9 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and ...
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CLKOUT Figure 4 provides the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 4. Synchronous Output Signals Timing Freescale Semiconductor Figure 3. External Clock Timing B8 ...
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Bus Signal Timing Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing Figure 6 provides the timing for ...
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CLKOUT TA D[0:31], DP[0:3] Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the ...
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Bus Signal Timing CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) 24 B11 B12 B8 B22 B25 B28 B18 MPC860 Family Hardware Specifications, Rev. 7 B23 B26 B19 Freescale Semiconductor ...
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CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) ...
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Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) Figure 13 through Figure 15 provide the timing for the external ...
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CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) Freescale Semiconductor B11 B12 B8 B22 B25 B26 B8 MPC860 Family Hardware Specifications, Rev. 7 Bus Signal ...
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Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) 28 B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 MPC860 Family ...
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CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) Figure 16 provides the timing for the external bus controlled by the UPM. Freescale Semiconductor B12 ...
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Bus Signal Timing CLKOUT B8 A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 16. External Bus Timing (UPM Controlled Signals) Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. 30 B31a B31d B31 B34 B34a ...
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CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] ...
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Bus Signal Timing CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM. CLKOUT AS ...
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Table 8 provides interrupt timing for the MPC860. Num Characteristic I39 IRQx valid to CLKOUT rising edge (setup time) I40 IRQx hold time after CLKOUT I41 IRQx pulse width low I42 IRQx pulse width high I43 IRQx edge-to-edge time 1 ...
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Bus Signal Timing Table 9 shows the PCMCIA timing for the MPC860. Num Characteristic P44 A(0:31), REG valid to PCMCIA 1 Strobe asserted P45 A(0:31), REG valid to ALE negation P46 CLKOUT to REG valid P47 CLKOUT to REG invalid ...
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CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 24. PCMCIA Access Cycle Timing External Bus Read Figure 25 provides the PCMCIA access cycle timing for the external bus write. Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 ...
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Bus Signal Timing CLKOUT TS A[0:31] REG CE1/CE2 PCWE, IOWR ALE D[0:31] Figure 25. PCMCIA Access Cycle Timing External Bus Write Figure 26 provides the PCMCIA WAIT signal detection timing. CLKOUT WAITx Figure 26. PCMCIA WAIT Signal Detection Timing Table ...
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Num Characteristic P57 CLKOUT to OPx valid P58 HRESET negated to OPx drive P59 IP_Xx valid to CLKOUT rising edge P60 CLKOUT rising edge to IP_Xx invalid 1 OP2 and OP3 only Figure 27 provides the PCMCIA output port timing ...
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Bus Signal Timing Num Characteristic P61 DSCK cycle time P62 DSCK clock pulse width P63 DSCK rise and fall times P64 DSDI input data setup time P65 DSDI data hold time P66 DSCK low to DSDO data valid P67 DSCK ...
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Table 12 shows the reset timing for the MPC860. Num Characteristic R69 CLKOUT to HRESET high impedance R70 CLKOUT to SRESET high impedance R71 RSTCONF pulse width R72 — R73 Configuration data to HRESET rising edge setup time R74 Configuration ...
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Bus Signal Timing HRESET RSTCONF D[0:31] (IN) Figure 31. Reset Timing—Configuration from Data Bus Figure 32 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 32. Reset Timing—Data Bus Weak ...
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CLKOUT SRESET DSCK, DSDI Figure 33. Reset Timing—Debug Port Configuration 10 IEEE 1149.1 Electrical Specifications Table 13 provides the JTAG timings for the MPC860 shown in Num J82 TCK cycle time J83 TCK clock pulse width measured at 1.5 V ...
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IEEE 1149.1 Electrical Specifications TCK TCK TMS, TDI TDO Figure 35. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 37. Boundary Scan (JTAG) Timing Diagram 42 J82 J83 J82 J84 Figure 34. ...
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CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC860. 11.1 PIP/PIO AC Electrical Specifications Table 14 provides the PIP/PIO AC timings as shown in Num 21 Data-in ...
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CPM Electrical Characteristics DATA-OUT STBO (Output) STBI (Input) Figure 39. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 40. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 41. PIP TX (Pulse Mode) ...
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CLKO DATA-IN DATA-OUT Figure 42. Parallel I/O Data-In/Data-Out Timing Diagram 11.2 Port C Interrupt AC Electrical Specifications Table 15 provides the timings for port C interrupts. Num 35 Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt ...
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CPM Electrical Characteristics Num 40 DREQ setup time to clock high 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high 43 SDACK negation delay from clock low 44 SDACK negation delay from TA low 45 ...
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CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 45. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 46. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA Freescale Semiconductor 42 46 ...
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CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 47. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 11.4 Baud Rate Generator AC Electrical Specifications Table 17 provides the baud rate generator timings as shown in Num ...
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Timer AC Electrical Specifications Table 18 provides the general-purpose timer timings as shown in Num 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid ...
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CPM Electrical Characteristics Num 75 L1RSYNC, L1TSYNC rise/fall time 76 L1RXD valid to L1CLK edge (L1RXD setup time) 77 L1CLK edge to L1RXD invalid (L1RXD hold time) 78 L1CLK edge to L1ST(1–4) valid 78A L1SYNC valid to L1ST(1–4) valid 79 ...
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L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RXD (Input) L1ST(4-1) (Output) Figure 50. SI Receive Timing Diagram with Normal Clocking (DSC = 0) Freescale Semiconductor 70 71a 72 RFSD BIT0 76 78 ...
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CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 51. SI Receive Timing with Double-Speed Clocking (DSC = 83a RFSD=1 77 ...
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L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4-1) (Output) Figure 52. SI Transmit Timing Diagram (DSC = 0) Freescale Semiconductor 70 72 TFSD 80a BIT0 80 78 MPC860 Family Hardware Specifications, ...
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CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 53. SI Transmit Timing with Double Speed Clocking (DSC = 83a ...
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Freescale Semiconductor Figure 54. IDL Timing MPC860 Family Hardware Specifications, Rev. 7 CPM Electrical Characteristics 55 ...
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CPM Electrical Characteristics 11.7 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing. Num 100 RCLK1 and TCLK1 width high 101 RCLK1 and TCLK1 width low 102 RCLK1 and TCLK1 rise/fall time 103 TXD1 active ...
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RCLK1 102 106 RxD1 (Input) CD1 (Input) CD1 (SYNC Input) Figure 55. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 56. SCC NMSI Transmit Timing Diagram Freescale Semiconductor 102 101 100 ...
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CPM Electrical Characteristics TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Echo Input) 11.8 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Num 120 CLSN width high 121 RCLK1 rise/fall time 122 RCLK1 width low 1 123 ...
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Num 134 TENA inactive delay (from TCLK1 rising edge) 135 RSTRT active delay (from TCLK1 falling edge) 136 RSTRT inactive delay (from TCLK1 falling edge) 137 REJECT width low 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK ...
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CPM Electrical Characteristics TCLK1 128 131 TxD1 (Output) 133 TENA(RTS1) (Input) RENA(CD1) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all ...
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SMC Transparent AC Electrical Specifications Table 23 provides the SMC transparent timings as shown in Num 1 150 SMCLK clock period 151 SMCLK width low 151A SMCLK width high 152 SMCLK rise/fall time 153 SMTXD active delay (from SMCLK ...
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CPM Electrical Characteristics Num 160 MASTER cycle time 161 MASTER clock (SCK) high or low time 162 MASTER data setup time (inputs) 163 Master data hold time (inputs) 164 Master data valid (after SCK edge) 165 Master data hold time ...
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SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 65. SPI Master ( Timing Diagram 11.11SPI Slave AC Electrical Specifications Table 25 provides the SPI slave timings as shown ...
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CPM Electrical Characteristics SPISEL (Input) SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 66. SPI Slave ( Timing Diagram 64 172 182 181 170 181 182 180 Data ...
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SPISEL (Input) 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 SPIMISO Undef (Output) 175 SPIMOSI (Input) Figure 67. SPI Slave ( Timing Diagram 2 11.12I C AC Electrical Specifications 2 Table 26 provides the I C ...
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CPM Electrical Characteristics Table 26. I Num 210 SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2). The ratio SYNCCLK/(BRGCLK / pre_scaler) must ...
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UTOPIA AC Electrical Specifications Table 28 shows the AC electrical specifications for the UTOPIA interface. Table 28. UTOPIA AC Electrical Specifications Num Signal Characteristic U1 UtpClk rise/fall time (Internal clock option) Duty cycle Frequency U1a UtpClk rise/fall time (external ...
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FEC Electrical Characteristics UtpClk U5 5 PHSELn TxClav HighZ at MPHY TxEnb UTPB SOC 13 FEC Electrical Characteristics This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing specifications for the MII signals ...
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MII_RX_CLK (Input) MII_RXD[3:0] (Inputs) MII_RX_DV MII_RX_ER Figure 71. MII Receive Signal Timing Diagram 13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum ...
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FEC Electrical Characteristics MII_TX_CLK (Input) MII_TXD[3:0] (Outputs) MII_TX_EN MII_TX_ER Figure 72. MII Transmit Signal Timing Diagram 13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 31 provides information on the MII async inputs signal timing. Num M9 MII_CRS, MII_COL minimum ...
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... MII_MDIO (Input) Figure 74. MII Serial Management Channel Timing Diagram 14 Mechanical Data and Ordering Information Table 33 provides information on the MPC860 Revision D.4 derivative devices. Table 33. MPC860 Family Revision D.4 Derivatives Device MPC855T MPC860DE MPC860DT MPC860DP Freescale Semiconductor Characteristic M14 M12 M13 Number of Ethernet Support 1 SCCs ...
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... MPC860DEZQ50D4 MPC860DTZQ50D4 MPC860ENZQ50D4 MPC860SRZQ50D4 MPC860TZQ50D4 MPC860DPZQ50D4 MPC860PZQ50D4 Tape and Reel MPC855TZQ50D4R2 MPC860DEZQ50D4R2 MPC860ENZQ50D4R2 MPC860SRZQ50D4R2 MPC860TZQ50D4R2 MPC860DPZQ50D4R2 Sample KMPC855TZQ50D4 KMPC860DEZQ50D4 KMPC860DTZQ50D4 KMPC860TZQ50D4 KMPC860SRZQ50D4 1 ZP/ZQ MPC855TZQ66D4 MPC860DEZQ66D4 MPC860DTZQ66D4 MPC860ENZQ66D4 MPC860SRZQ66D4 MPC860TZQ66D4 MPC860DPZQ66D4 MPC860PZQ66D4 Tape and Reel MPC860SRZQ66D4R2 MPC860PZQ66D4R2 Freescale Semiconductor ATM N/A Yes Yes Yes ...
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... KMPC860ENZQ66D4 KMPC860PZQ66D4 1 ZP/ZQ MPC855TZQ80D4 MPC860DEZQ80D4 MPC860DTZQ80D4 MPC860ENZQ80D4 MPC860SRZQ80D4 MPC860TZQ80D4 MPC860DPZQ80D4 MPC860PZQ80D4 Tape and Reel MPC860PZQ80D4R2 Sample KMPC855TZQ80D4 KMPC860DEZQ80D4 KMPC860DTZQ80D4 KMPC860ENZQ80D4 KMPC860SRZQ80D4 KMPC860TZQ80D4 KMPC860DPZQ80D4 KMPC860PZQ80D4 1 ZP/ZQ MPC855TCZQ50D4 MPC860DECZQ50D4 MPC860DTCZQ50D4 MPC860ENCZQ50D4 MPC860SRCZQ50D4 MPC860TCZQ50D4 MPC860DPCZQ50D4 MPC860PCZQ50D4 Tape and Reel MPC855TCZQ50D4R2 1 ZP/ZQ MPC855TCZQ66D4 MPC860ENCZQ66D4 MPC860SRCZQ66D4 MPC860TCZQ66D4 MPC860DPCZQ66D4 MPC860PCZQ66D4 73 ...
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Mechanical Data and Ordering Information 14.1 Pin Assignments Figure 75 shows the top view pinout of the PBGA package. For additional information, see the MPC860 PowerQUICC User’s Manual, or the MPC855T User’s Manual. NOTE: This is the top view of ...
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TOP VIEW ...
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Mechanical Data and Ordering Information 1. All Dimensions in millimeters 2. Dimensions and tolerance per ASME Y14.5M, 1994 3. Maximum Solder Ball Diameter measured parallel to Datum A Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature 76 NOTE of the ...
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Document Revision History Table 35 lists significant changes between revisions of this hardware specification. Revision Date 5.1 11/2001 • Revised template format, removed references to MAC functionality, changed B23 max value @ 66 MHz from 2ns to 8ns, added ...
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Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK 78 MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor ...
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THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor MPC860 Family Hardware Specifications, Rev. 7 Document Revision History 79 ...
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