MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 59

• Manufacturer Part Number: MPC860DP
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
1
2
Num
134
135
136
137
138
139
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
RENA(CD1)
CLSN(CTS1)
TENA inactive delay (from TCLK1 rising edge)
RSTRT active delay (from TCLK1 falling edge)
RSTRT inactive delay (from TCLK1 falling edge)
REJECT width low
CLKO1 low to SDACK asserted
CLKO1 low to SDACK negated
RCLK1
(Input)
(Input)
RxD1
(Input)
Figure 58. Ethernet Collision Timing Diagram
Figure 59. Ethernet Receive Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
Table 22. Ethernet Timing (continued)
Characteristic
2
2
121
124
120
125
121
126
Min
All Frequencies
10
10
10
—
—
1
123
CPM Electrical Characteristics
Last Bit
127
Max
50
50
50
20
20
—
Unit
CLK
ns
ns
ns
ns
ns
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