MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 33

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MPC860DP

Manufacturer Part Number
MPC860DP
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Table 8
Figure 22
Figure 23
Freescale Semiconductor
1
level-sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC860 is able to support.
Num
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
I39
I40
I41
I42
I43
provides interrupt timing for the MPC860.
provides the interrupt detection timing for the external level-sensitive lines.
provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
CLKOUT
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
IRQx
IRQx
Figure 22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines
Characteristic
MPC860 Family Hardware Specifications, Rev. 7
Table 8. Interrupt Timing
1
I39
I43
I41
I40
4 × T
I43
CLOCKOUT
6.00
2.00
3.00
3.00
Min
All Frequencies
I42
Max
Bus Signal Timing
Unit
ns
ns
ns
ns
33

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