LTC2440 Linear Technology, LTC2440 Datasheet

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LTC2440

Manufacturer Part Number
LTC2440
Description
24-Bit High Speed Differential delta-sigma ADC
Manufacturer
Linear Technology
Datasheet

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APPLICATIO S
FEATURES
TYPICAL APPLICATIO
Up to 3.5kHz Output Rate
Selectable Speed/Resolution
2µV
200nV
Simultaneous 50/60Hz Rejection
0.0005% INL, No Missing Codes
Autosleep Enables 20µA Operation at 6.9Hz
< 5µV Offset (4.5V < V
Differential Input and Differential Reference with
GND to V
No Latency, Each Conversion is Accurate Even After
an Input Step
Internal Oscillator—No External Components
Pin Compatible with the LTC2410
24-Bit ADC in Narrow 16-Lead SSOP Package
High Speed Multiplexing
Weight Scales
Auto Ranging 6-Digit DVMs
Direct Temperature Measurement
High Speed Data Acquisition
REFERENCE VOLTAGE
–0.5V
RMS
ANALOG INPUT
REF
RMS
0.1V TO V
TO 0.5V
Noise at 880Hz Output Rate
CC
Noise at 6.9Hz Output Rate with
Common Mode Range
Simple 24-Bit 2-Speed Acquisition System
4.5V TO 5.5V
REF
1, 8, 9, 16
CC
U
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
+
CC
LTC2440
+
< 5.5V, – 40°C to 85°C)
BUSY
SDO
SCK
EXT
SDI
CS
F
O
U
15
14
13
12
11
7
10
2440 TA01
3-WIRE
SPI INTERFACE
V
CC
6.9Hz, 200nV NOISE,
50/60Hz REJECTION
880Hz OUTPUT RATE,
2µV NOISE
2440 TA01
Selectable Speed/Resolution
10-SPEED SERIAL
PROGRAMMABLE
DESCRIPTIO
The LTC
with 5ppm INL and 5µV offset. It uses proprietary delta-
sigma architecture enabling variable speed and resolution
with no latency. Ten speed/resolution combinations (6.9Hz/
200nV
a simple serial interface. Alternatively, by tying a single pin
HIGH or LOW, a fast (880Hz/2µV
(6.9Hz, 200nV
combination can be easily selected. The accuracy (offset,
full-scale, linearity, drift) and power dissipation are inde-
pendent of the speed selected. Since there is no latency,
a speed/resolution change may be made between conver-
sions with no degradation in performance.
Following each conversion cycle, the LTC2440 automati-
cally enters a low power sleep state. Power dissipation
may be reduced by increasing the duration of this sleep
state. For example, running at the 3.5kHz conversion
speed but reading data at a 100Hz rate draws 240µA
average current (1.1mW) while reading data at a 7Hz
output rate draws only 25µA (125µW).The LTC2440 com-
municates through a flexible 3-wire or 4-wire digital inter-
face that is compatible with the LTC2410 and is available
in a narrow 16-lead SSOP package.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Differential ∆Σ ADC with
RMS
®
2440 is a high speed 24-bit No Latency ∆Σ
to 3.5kHz/25µV
RMS
100
0.1
10
, 50/60Hz rejection) speed/resolution
1
24-Bit High Speed
U
1
(50/60Hz REJECTION)
V
V
V
CC
REF
IN
200nV AT 6.9Hz
+
= 5V
= V
= 5V
RMS
Speed vs RMS Noise
IN
10
CONVERSION RATE (Hz)
= 0V
2µV AT 880Hz
) are programmed through
RMS
100
) or ultralow noise
LTC2440
1000
2440 TA02
sn2440, 2440fas
10000
TM
ADC
1

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LTC2440 Summary of contents

Page 1

... LTC2440 com- municates through a flexible 3-wire or 4-wire digital inter- face that is compatible with the LTC2410 and is available in a narrow 16-lead SSOP package ...

Page 2

... Digital Input Voltage to GND ........ – 0. Digital Output Voltage to GND ..... – 0. Operating Temperature Range LTC2440C ............................................... 0°C to 70°C LTC2440I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T ...

Page 3

... CC 0V ≤ V ≤ ≤ V ≤ V (Note (Note –800µ 1.6mA –800µA (Note 1.6mA (Note 9) O LTC2440 MIN TYP MAX ● GND – 0. 0.3V CC ● GND – 0. 0.3V CC ● – REF REF ● 0 ● ...

Page 4

... LTC2440 W U POWER REQUIRE E TS otherwise specifications are 25°C. (Note 3) A SYMBOL PARAMETER V Supply Voltage CC I Supply Current CC Conversion Mode Sleep Mode CHARACTERISTICS range, otherwise specifications are at T SYMBOL PARAMETER f External Oscillator Frequency Range EOSC t External Oscillator High Period ...

Page 5

... REF 25°C REF A – GND REF 5 0 –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 V (V) IN 2440 G08 LTC2440 Integral Nonlinearity f = 880Hz OUT 2.5V CC INCM GND REF 25°C REF A – GND REF 5 0 –5 – ...

Page 6

... LTC2440 W U TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity f = 6.875Hz OUT 2.5V CC INCM GND REF 25°C REF A – GND 5 REF 0 –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 V (V) IN 2440 G10 Integral Nonlinearity vs Temperature 1.25V ...

Page 7

... CLOCK 20MHz REF CC TEMP = 25°C 2 SWEEP (V – REF REF 0 2000 2500 3000 3500 4000 OUTPUT RATE (Hz) 2440 G26 LTC2440 Offset Error 5 2.5V OSR = 32768 REF + GND REF O – GND T = 25°C REF A + – GND 2 ...

Page 8

... LTC2440 CTIO S GND (Pins 16): Ground. Multiple ground pins internally connected for optimum ground current flow and V decoupling. Connect each one of these pins to a ground CC plane through a low impedance connection. All four pins must be connected to ground for proper operation. ...

Page 9

... U APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2440 is a high speed, delta-sigma analog-to- digital converter with an easy to use 4-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2) ...

Page 10

... These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2440 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy ...

Page 11

... Output Data Format The LTC2440 serial output data stream is 32-bits long. The first 3-bits represent status information indicating the sign and conversion state. The next 24-bits are the conversion result, MSB first. The remaining 5-bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution ...

Page 12

... SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2440 creates its own serial clock. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected by tying EXT (Pin 10) LOW for external SCK and HIGH for internal SCK ...

Page 13

... In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2440 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i ...

Page 14

... **Address allows tying SDI HIGH *Additional address to allow tying SDI LOW Table 4. LTC2440 Interface Timing Modes Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion OSR3 ...

Page 15

... Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. Conversely, BUSY (Pin 15) may be used to monitor the status of the conversion cycle. EOC or BUSY may be used as an interrupt to an external controller LTC2440 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 3-WIRE SPI INTERFACE ...

Page 16

... REF SDI GND EXT TEST EOC BIT 31 BIT 30 BIT 29 EOC SIG Hi-Z Hi-Z SLEEP DATA OUTPUT 4.5V TO 5.5V 1µ BUSY CC LTC2440 REF F O REFERENCE VOLTAGE – SCK CC REF SDO IN ANALOG INPUT RANGE 6 11 –0.5V TO 0.5V – REF ...

Page 17

... EXT BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 SIG MSB DATA OUTPUT Figure 8. Internal Serial Clock, Single Cycle Operation LTC2440 after the falling edge of CS EOCtest after EOC goes LOW ( LOW EOCtest EOCtest , the first rising EOCtest = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 3-WIRE ...

Page 18

... The part remains in the sleep state a minimum amount of time (≈500ns) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and 4.5V TO 5.5V 1µ BUSY V CC LTC2440 REF O REFERENCE VOLTAGE – ...

Page 19

... grounded 1.8MHz ±5% (over supply and temperature variations OSR of 32,768, the first NULL latency output rate where Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator) N LTC2440 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 2-WIRE SPI INTERFACE V CC 200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2µ ...

Page 20

... F12 Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator) occurs at 55Hz • 32,768 = S = 7.04kHz with an OSR of 256 N grounded. While the – ...

Page 21

... LTC2440, the speed/resolution/power dissipation may also be adjusted using the automatic sleep mode. During near DC while N the conversion cycle, the LTC2440 draws 8mA supply current independent of the programmed speed. Once the conversion cycle is completed, the device automatically enters a low power sleep state drawing 8µA. The device remains in this state as long HIGH and data is not shifted out ...

Page 22

... Because of the small current pulses, excessive lead length at the analog or reference input may allow reflections or ringing to occur, affecting the conversion accuracy. The key to preserving the accuracy of the LTC2440 is complete settling of these sampling glitches at both the input and reference terminals. There are several recommended methods of doing this ...

Page 23

... V + REF CC suitability of an amplifier for use with the LTC2440 is suggested here: 1. Perform a thorough error and noise analysis on the 2440 F18 amplifier and gain setting components to verify that the amplifier will perform as intended. 2. Measure the large signal response of the overall circuit. ...

Page 24

... C4 – + IN– LTC2051HV 2 Figure 19. Buffering the LTC2440 from High Impedance Sources Using A Chopper Amplifier 100µs/DIV Figure 20. Large Signal Input Settling Time Indicates Completed Settling with Selected Load Capacitance For more information on testing high linearity ADCs, refer to Linear Technology Design Solutions 11. ...

Page 25

... ADC will reject wideband input noise up to the modulator sample rate. The example portion of the digital on the following page shows how the noise rejection of the LTC2440 reduces the effective noise of an amplifier driv- ing its input. First Notch Frequency External ...

Page 26

... Ultralow noise applications may require the use of low noise bipolar amplifiers that are not autozeroed. Because the LTC2440 has such exceptionally low offset, offset drift and 1/f noise, the offset drift and 1/f noise in the amplifiers may need to be compensated for to retain the system performance of which the ADC is capable ...

Page 27

... IN SPI INTERFACE 6 11 – SDI GND EXT Figure 22. Simple External Clock Source LTC2440 .189 – .196* (4.801 – 4.978) .009 (0.229 REF .150 – .157** (3.810 – 3.988 .004 – .0098 (0.102 – ...

Page 28

... RMS 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/ LTC2404/LTC2408 www.linear.com ● V REF 10µF 0.1µF + REF + IN 1µF LTC2440 – IN 1µF – REF 2440 F22 Noise P-P Noise 0.01Hz to 10Hz P-P Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection Noise, 6ppm INL sn2440, 2440fas LT/TP 0105 REV A • PRINTED IN USA ...

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