LTC2440 Linear Technology, LTC2440 Datasheet - Page 19

• Manufacturer Part Number: LTC2440
• Description: 24-Bit High Speed Differential delta-sigma ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
ends after the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2440 significantly
simplifies antialiasing filter requirements.
The LTC2440’s speed/resolution is determined by the over
sample ratio (OSR) of the on-chip digital filter. The OSR
ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz
output rate. The value of OSR and the sample rate f
determine the filter characteristics of the device. The first
NULL of the digital filter is at f
(INTERNAL)
BUSY
SDO
SCK
CS
CONVERSION
U
BIT 31
EOC
U
N
SLEEP
BIT 30
and multiples of f
Figure 10. Internal Serial Clock, Continuous Operation
W
ANALOG INPUT RANGE
REFERENCE VOLTAGE
–0.5V
BIT 29
SIG
REF
0.1V TO V
TO 0.5V
U
BIT 28
MSB
1µF
REF
4.5V TO 5.5V
CC
N
1, 8, 9, 16
where
2
3
4
5
6
BIT 27
V
REF
REF
IN
IN
GND
S
CC
+
–
LTC2440
+
–
DATA OUTPUT
f
frequency f
If F
1.8MHz ±5% (over supply and temperature variations). At
an OSR of 32,768, the first NULL is at f
latency output rate is f
BUSY
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
BIT 26
N
SDO
SCK
EXT
SDI
CS
F
= f
O
O
15
14
13
12
11
10
7
S
is grounded, f
/OSR, see Figure 11 and Table 5. The rejection at the
V
CC
–120
–140
–100
–20
–40
–60
–80
2-WIRE
SPI INTERFACE
N
0
V
CC
±14% is better than 80dB, see Figure 12.
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2µV NOISE, 880Hz OUTPUT RATE
LSB
BIT 5
24
60
S
N
is set by the on-chip oscillator at
/8 = 6.9Hz. At the maximum OSR,
120
BIT 0
180
N
= 55Hz and the no
2440 F11
LTC2440
CONVERSION
240
sn2440, 2440fas
2410 F10
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