LTC2440 Linear Technology, LTC2440 Datasheet - Page 21

• Manufacturer Part Number: LTC2440
• Description: 24-Bit High Speed Differential delta-sigma ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
The sample rate f
driving the F
rate is f
clock applied to F
sample rate leads to notch frequencies f
maintaining simple antialiasing requirements. A 100kHz
clock applied to F
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 22. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
The normal mode rejection characteristic shown in Fig-
ure 14 is achieved by applying the output of the LTC1799
(with R
tied HIGH (OSR = 32768).
f
OSC
SET
S
=
= f
10
= 100k) to the F
O
EOSC
MHz
pin with an external oscillator. The sample
O
/5, where f
S
. Combining a large OSR with a reduced
•
O
U
and NULL f
⎛
⎜
⎝
results in a NULL at 0.6Hz plus all
10
10
•
R
U
k
SET
O
pin on the LTC2440 with SDI
EOSC
⎞
⎟
⎠
N
, my also be adjusted by
is the frequency of the
W
–120
–140
–100
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
N
–20
–40
–60
–80
0
near DC while
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
U
2
4
Reduced Power Operation
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8µA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
For example, if the OSR is programmed at the fastest rate
(OSR = 64, t
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240µA. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30µA. Noise, power, and
speed can be optimized by adjusting the OSR (Noise/
Speed) and sleep mode duration (Power).
6
8
2440 F14
CONV
10
= 0.285ms) and the sleep state is 10ms,
LTC2440
sn2440, 2440fas
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