ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 30

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

The Timer/Counter1 Control
Register – TCCR1
30
ATtiny15L
value, lower than $FF. Together with the many prescaler options, flexible PWM fre-
quency selection is provided. Table 14 lists clock selection and OCR1B values to obtain
PWM frequencies from 10 kHz to 150 kHz at 10 kHz steps.
• Bit 7 – CTC1: Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock
cycle after a compare match with OCR1A register value. If the control bit is cleared,
Timer/Counter1 continues counting and is unaffected by a compare match.
• Bit 6 – PWM1: Pulse Width Modulator Enable
When set (one), this bit enables PWM mode for Timer/Counter1. This mode is described
on page 31.
• Bits 5,4 – COM1A1, COM1A0: Compare Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a
compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since
this is an alternative function to an I/O port, the corresponding direction control bit must
be set (one) to control an output pin. The control configuration is shown in Table 10.
Table 10. Compare Mode Select
Note:
• Bits 3, 2, 1, 0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
Table 11. Timer/Counter1 Prescale Select
Bit
$30
Read/Write
Initial Value
COM1A1
CS13
0
0
0
0
0
0
0
0
0
0
1
1
1. In PWM mode, these bits have a different function. Refer to Table 12 for a detailed
description.When changing the COM1A1/COM1A0 bits, the Output Compare 1A
Interrupt must be disabled by clearing its Interrupt Enable bit in the TIMSK Register.
Otherwise an interrupt can occur when the bits are changed.
CTC1
R/W
7
0
CS12
COM1A0
0
0
0
0
1
1
1
1
0
1
0
1
PWM1
R/W
6
0
CS11
0
0
1
1
0
0
1
1
Description
Timer/Counter disconnected from output pin OC1A
Toggle the OC1A output line.
Clear the OC1A output line (to zero).
Set the OC1A output line (to one).
COM1A1
R/W
5
0
(1)
CS10
COM1A0
R/W
0
1
0
1
0
1
0
1
4
0
Description
Timer/Counter1 is stopped.
CK*16 (=PCK)
CK*8 (=PCK/2)
CK*4 (=PCK/4)
CK*2 (=PCK/8)
CK
CK/2
CK/4
CS13
R/W
3
0
CS12
R/W
2
0
CS11
R/W
1
0
CS10
R/W
0
0
1187D–12/01
TCCR1