ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 18

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

Internal Voltage
Reference
Voltage Reference Enable
Signals and Start-up Time
Interrupt Handling
18
ATtiny15L
• Bit 1 – EXTRF: External Reset Flag
This bit is set (one) if a External Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logical “0” to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set (one) if a Power-on Reset occurs. The bit is reset (zero) by writing a logical
“0” to the flag.
To make use of the reset flags to identify a reset condition, the user should read and
then reset the MCUSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the reset
flags.
ATtiny15L features an internal bandgap reference with a nominal voltage of 1.22V. This
reference is used for Brown-out Detection, and it can be used as an input to the Analog
Comparator. The 2.56V reference to the ADC is generated from the internal bandgap
reference.
The voltage reference has a start-up time that may influence the way it should be used.
The maximum start-up time is TBD. To save power, the reference is not always turned
on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODEN fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the AINBG bit, the user must always
allow the reference to start-up before the output from the Analog Comparator is used.
The bandgap reference uses typically 10 µA, and to reduce power consumption in
Power-down mode, the user can avoid the three conditions above to ensure that the ref-
erence is turned off before entering Power-down mode.
The ATtiny15L has two 8-bit Interrupt Mask control registers: GIMSK (General Interrupt
Mask register) and TIMSK (Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set the I-bit (one) to enable interrupts. The I-
bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is present.
the AINBG bit in ACSR).
1187D–12/01