ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 44

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 27. ADC Timing Diagram, First Conversion (Single Conversion Mode)
44
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
ATtiny15L
1
2
MUX and REFS
Update
12
the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running
for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following rising edge of the ADC clock cycle. If differential channels are selected, the
conversion will only start at every other rising edge of the ADC clock cycle after ADEN
was set.
A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs
more clock cycles to perform initialization and minimize offset errors. These extended
conversions take 25 ADC clock cycles and occur as the first conversion after one of the
following events:
•
•
•
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 13.5 ADC clock cycles after the start of an extended conversion. When
a conversion is complete, the result is written to the ADC data registers, and ADIF is set.
In Single Conversion mode, ADSC is cleared simultaneously. The software may then
set ADSC again, and a new conversion will be initiated on the first rising ADC clock
edge. In Free Running mode, a new conversion will be started immediately after the
conversion completes while ADSC remains high. Using Free Running mode and an
ADC clock frequency of 200 kHz gives the lowest conversion time, 65
15 kSPS. For a summary of conversion times, see Table 18.
13
the ADC is switched on (ADEN in ADCSR is set)
the voltage reference source is changed (the REFS1..0 bits in ADMUX change
value)
a differential channel is selected (MUX2 in ADMUX is “1”). Note that subsequent
conversions on the same channel are not extended conversions.
14
15
Sample & Hold
16
Extended Conversion
17
18
19
20
21
22
Conversion
Complete
23
24
25
Sign and MSB of Result
Next
Conversion
1
LSB of Result
µs
, equivalent to
2
MUX and REFS
Update
1187D–12/01
3