HW-XGI-SCLK-G Xilinx Inc, HW-XGI-SCLK-G Datasheet - Page 8

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HW-XGI-SCLK-G

Manufacturer Part Number
HW-XGI-SCLK-G
Description
MODULE SUPER CLOCK
Manufacturer
Xilinx Inc
Datasheet

Specifications of HW-XGI-SCLK-G

Accessory Type
Clock
For Use With/related Products
ML423, ML521, ML523, ML525
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Introduction
8
Reference Clock Selection, J13
Power Supply Option Headers
Control Switch, SW1
Master Reset, SW2
Off = Logic 0
On = Logic 1
Note:
Figure 1
Note:
the board.
XTAL1
XTAL0
Images are intended for reference purposes only and might not reflect the current version of
= Pin 1
and
Figure 1: SuperClock Module, Front View
Figure 2: SuperClock Module, Back View
100Ω SMA Clock Pairs:
Figure 2
External Board Interface Connectors
CLK0, J2 and J3
CLK1, J4 and J5
CLK2, J6 and J7
show the front and back views of the SuperClock module.
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N0
N1
N2
M0
M1
M2
SEL0
SEL1
MR
J1 (2 x 32)
J11 (1 x 32)
5V DC Input
Xilinx Generic Interface (XGI) SuperClock Module
UG091_02_062705
Test Clock, J10
UG091 (v1.1) March 2, 2007
UG091_01_062705
Reference
Clock, J8
R

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