HW-XGI-SCLK-G Xilinx Inc, HW-XGI-SCLK-G Datasheet - Page 12

• Manufacturer Part Number: HW-XGI-SCLK-G
• Description: MODULE SUPER CLOCK
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-SCLK-G

• Accessory Type: Clock
• For Use With/related Products: ML423, ML521, ML523, ML525
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
12
Table 5: Common Configurations (Continued)
The resultant output frequency is delivered by way of differential pair Q0 and NQ0 to a
1-to-4 differential LVDS fan-out buffer. This establishes three, 100Ω differential pair
outputs at CLK0, CLK1, and CLK2, and is A/C coupled to corresponding SMA pairs (J2,
J3), (J4, J5), and (J6, J7), respectively.
The REF_CLK output at SMA J8 is enabled when the reference clock output enable
(REF_OE) at J13 is pulled High or when a jumper is placed across pins 1 and 2 of J13. With
REF_OE enabled, the differential outputs are disabled. For normal operation, leave J13
open.
Notes: User Tips
1. REF_CLK * M divider value = VCO frequency
2. VCO Frequency / N Divider = Output frequency
Reference
19.53125
26.5625
26.5625
26.5625
Clock
Input
19.44
31.25
20
25
25
25
25
Divider
32
32
25
25
25
24
24
24
24
24
18
M
Divider
www.xilinx.com
N
2
4
2
2
5
6
4
6
3
4
3
(MHz)
622.08
637.5
637.5
637.5
562.5
VCO
625
500
625
625
600
600
Xilinx Generic Interface (XGI) SuperClock Module
Frequency
Output
159.375
(MHz)
311.04
156.25
106.25
312.5
212.5
187.5
250
125
100
150
SONET
10-Gigabit Ethernet
Ethernet, PCI Express
10-Gigabit Ethernet
1-Gigabit Ethernet
PCI Express
SATA
Fibre Channel 1
4-Gigabit Fibre Channel
10-Gigabit Fibre Channel
12-Gigabit Ethernet
UG091 (v1.1) March 2, 2007
Application
R