HW-XGI-SCLK-G Xilinx Inc, HW-XGI-SCLK-G Datasheet - Page 10

• Manufacturer Part Number: HW-XGI-SCLK-G
• Description: MODULE SUPER CLOCK
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-SCLK-G

• Accessory Type: Clock
• For Use With/related Products: ML423, ML521, ML523, ML525
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
10
The LVPECL frequency synthesizer receives a stable fundamental frequency from one of
two populated crystal oscillators (XTAL0, XTAL1) or by using the test clock input at SMA
J10. Reference clock input selection is set according to the input state of SEL0 and SEL1 as
defined in
Table 2: Reference Clock Selection
The feedback divider, using the states of M0, M1, and M2 as defined in
the VCO output frequency. Floating inputs result in a default divisor of 32.
Table 3: M Divider Selection
The reference clock output is divided by the states of inputs N0, N1, and N2 as defined in
Table
Table 4: N Divider Selection
SEL0
M0
N0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4. Floating inputs result in a default divisor of 4.
Inputs
Inputs
Inputs
Table
SEL1
M1
N1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
2.
XTAL0
XTAL1
TEST_CLK
TEST_CLK
M2
N2
0
0
0
0
1
1
0
0
0
0
1
1
Reference
www.xilinx.com
M Divider Value
N Divider Value
18
22
24
25
32
40
1
2
3
4
5
6
Active
Active
Active
Bypass
PLL Mode
Xilinx Generic Interface (XGI) SuperClock Module
Minimum
27.22
22.27
20.41
19.60
15.31
12.25
Input Frequency
UG091 (v1.1) March 2, 2007
Table
Maximum
3, determines
35.56
29.09
26.67
25.60
20.00
16.00
R