KS8695P-EVAL Micrel Inc, KS8695P-EVAL Datasheet - Page 15

• Manufacturer Part Number: KS8695P-EVAL
• Description: BOARD EVAL EXPERIMENT KS8695P
• Manufacturer: Micrel Inc

Specifications of KS8695P-EVAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1002

KS8695P
Micrel
Functional Description
Introduction
Micrel's KS8695P, a member of the CENTAUR line of integrated processors, is a high-performance router-on-a-chip solu-
tion for Ethernet and 802.11 a/g/b based embedded systems. Designed for use in communication's routers, it integrates a
PCI to AHB bridge solution for interfacing with 32-bit PCI, miniPCI, and cardbus devices. The KS8695P combines a proven
third generation 5-port managed switch, an ARM9 RISC processor with MMU, and five physical layer transceivers (PHYs)
including their corresponding MAC units with Micrel's XceleRouter technology.
The KS8695P is built around the 16/32-bit ARM9 RISC processor, which is a scalable, high-performance, microprocessor
developed for highly integrated system-on-a-chip applications. It also offers a configurable 8KB I-cache and 8KB D-cache
that reduces memory access latency for high-performance applications. The simple, elegant, and fully static design of the
KS8695P is especially suitable for cost-effective, power-sensitive applications.
The KS8695P contains five 10/100 PHYs: four are for the local area network (LAN) and one is for the wide area network
(WAN). Connected to the PHYs are five corresponding MAC units with an integrated Layer 2 managed switch. The combining
of the switch and the analog PHYs make the KS8695P an extremely prudent solution for SOHO router applications, saving
both board space and BOM costs. The Layer 2 switch contains a 16Kx32 SRAM on-chip memory for frame buffering. The
embedded frame buffer memory is designed with a 1.4Gbps on-chip memory bus. This allows the KS8695P to perform full
non-blocking frame switching and/or routing on the fly for many applications
For the media interface, the KS8695P supports 10BASE-T and 100BASE-TX, as specified by the IEEE 802.3 standard, and
100 BASE-FX on the WAN port and on one LAN port
The KS8695P supports two modes of operation in the PCI bus environment: host bridge mode and guest bridge mode. In the
host bridge mode, the ARM9 processor acts as the host of the entire system. It configures other PCI devices and coordinates
their transactions, including initiating transactions between the PCI devices and AHB bus subsystem. An on-chip PCI arbiter
is included to determine the PCI bus ownership among PCI master devices. In host bridge mode, all I/O registers, including
those for the embedded switch, are configured by the ARM9 processor through the on-chip AMBA bus interface.
In guest bridge mode, all of the I/O registers are programmed by either the external host CPU on the PCI bus or the local
ARM9 host processor through the AMBA bus. The KS8695P functions as a slave on the PCI bus with the on-chip PCI arbiter
disabled. The KS8695PX can be configured by either the ARM9 CPU or the PCI host CPU. In both cases, the KS8695P
memory subsystem is accessible from either the PCI host or the ARM9 CPU. Communications between the external host
CPU and the ARM9 is accomplished through message passing or through shared memory.
CPU Features
• 166MHz ARM9 RISC processor core
• On-chip AMBA bus 2.0 interfaces
• 16-bit thumb programming to relax memory requirement
• 8KB I-cache and 8KB D-cache
• Little-endian mode supported
• Configurable memory management unit
• Supports reduced CPU and system clock speed for power savings
PCI to AHB Bridge Features
• Support 33MHz, 32-bit data PCI bus
• Integrated PCI bridge support for interfacing with 32-bit miniPCI or cardbus devices
• Independent AHB and PCI clock speed
• Supports 125MHz AHB speed
• Supports PCI revision 2.1 protocols
• Supports AHB bus 2.0 interfaces
• Supports both regular and memory-mapped I/O on the PCI interface
• Integrated PCI arbiter with power-on option to enable or disable
• Support Round Robin arbitration with three external PCI devices and one internal device
• Supports AHB burst transfers up to 16 data words
• Configurable PCI registers by host CPU ARM9
• Supports bus mastership from PCI to AHB or AHB to PCI bus
Switch Engine
• 5-Port 10/100 integrated switch with one WAN and four LAN physical layer transceivers
• 16Kx32 on-chip SRAM for frame buffering
• 1.4Gbps on-chip memory bandwidth for wire-speed frame switching
• 10Mbps and 100Mbps modes of operation for both full and half duplex
August 2005
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M9999-081805