KS8695P-MDP-EVAL Micrel Inc, KS8695P-MDP-EVAL Datasheet
KS8695P-MDP-EVAL
Specifications of KS8695P-MDP-EVAL
Related parts for KS8695P-MDP-EVAL
KS8695P-MDP-EVAL Summary of contents
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... General Description The CENTAUR KS8695P, Multi-Port PCI Gateway Solution, delivers a new level of networking integration, performance, and overall BOM cost savings, enabling original equipment manufacturers (OEMs) to provide customers with feature-rich, low-cost solutions for the residential gateway and small office environment. • Integration of a PCI arbiter supporting three external masters. – ...
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... Low-power Ethernet transceivers – Per port power-down and Ethernet transmit disable – Hardware evaluation board (passes class B EMI) – Board support package including firmware source codes, Linux kernel, and software stacks – Complete hardware and software reference designs available KS8695P M9999-051806 ...
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... Added wireless applications. Added Pb-Free and industrial specification. Edits to Pin Description Table. 1.5 05/18/06 Added Pb-Free option for industrial specification. May 2006 Temperature Package Range 0° to +70°C 289-Pin PBGA Temperature Package Range –40° to +85°C 289-Pin PBGA 3 KS8695P M9999-051806 ...
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... System Level Hardware Interfaces................................................................................................................................... 18 Configuration Pins ............................................................................................................................................................ 18 Reset................................................................................................................................................................................. 19 System Clock.................................................................................................................................................................... 20 Memory Interface.............................................................................................................................................................. 21 Signal Descriptions by Group ........................................................................................................................................... 25 Address Map and Register Description............................................................................................................................ 35 Memory Map ..................................................................................................................................................................... 35 Memory Map Example...................................................................................................................................................... 35 Register Description ......................................................................................................................................................... 35 Absolute Maximum Ratings ............................................................................................................................................... 36 Operating Ratings ............................................................................................................................................................... 36 Electrical Characteristics ................................................................................................................................................... 36 Timing Diagrams ................................................................................................................................................................. 38 Package Information........................................................................................................................................................... 42 May 2006 4 KS8695P M9999-051806 ...
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... Micrel, Inc. System Level Applications May 2006 Figure 1. KS8695P PCI Gateway System Options 5 KS8695P M9999-051806 ...
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... PCI Commands and Byte Enable 2. Active Low. I/O PCI Commands and Byte Enable 3. Active Low. I/O Cardbus Clock Run Request Signal. Active Low. I/O External Data Bit. I/O External Data Bit. I/O External Data Bit. I/O External Data Bit. 6 KS8695P M9999-051806 ...
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... ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1, Active Low. O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low. O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low. O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low. 7 KS8695P M9999-051806 ...
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... General Purpose I/O Pin. External Interrupt Request Pin. I/O General Purpose I/O Pin. External Interrupt Request Pin. I/O General Purpose I/O Pin. I/O General Purpose I/O Pin. I/O General Purpose I/O Pin. I/O General Purpose I/O Pin. I/O General Purpose I/O Pin. 8 KS8695P M9999-051806 ...
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... LAN Port 4 PHY Transmit Signal – (differential). O LAN Port 1 PHY Transmit Signal + (differential). O LAN Port 2 PHY Transmit Signal + (differential). O LAN Port 3 PHY Transmit Signal + (differential). O LAN Port 4 PHY Transmit Signal + (differential). I PCI 66 MHz Enable. O MiniPCI Active Signal. Active Low. I/O PCI Address and Data 0. 9 KS8695P M9999-051806 ...
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... PCI Bridge Mode Select. ‘1’ = Host Bridge Mode. ‘0’ = Guest Bridge Mode. I PCI Bus Clock. O PCI Clock Output 0. O PCI Clock Output 1. O PCI Clock Output 2. O PCI Clock Output 3. I/O PCI Parity Error Signal. Active Low. I PCI Reset. Active Low. 10 KS8695P M9999-051806 ...
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... PCI Bus Request 2. Active Low. Input for Host Bridge Mode, Not Used in Guest Bridge Mode. I PCI Bus Request 3. Active Low. Input for Host Bridge Mode, Not Used in Guest Mode I KS8695P Chip Reset. Active Low. O SDRAM Column Address Strobe. Active Low. O SDRAM Chip Select. Active Low Chip Select Pins for SDRAM. O SDRAM Chip Select ...
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... Digital I/O Circuitry V P 3.3V Digital I/O Circuitry V P 3.3V Digital I/O Circuitry V P 3.3V Digital I/O Circuitry V P 3.3V Digital I/O Circuitry V P 3.3V Digital I/O Circuitry V P 3.3V Digital I/O Circuitry V P 3.3V Digital I/O Circuitry KS8695P M9999-051806 ...
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... WAN PHY Transmit Signal + (differential). O/I WAN LED Programmable Indicator 0. Bank 0 Size Bit 0. O/I WAN LED Programmable Indicator 1. Bank 0 Size Bit 1. O Watchdog Timer Reset Output. When EROEN/WRSTPLS = 0, Active High. When EROEN/WRSTPLS = 1, Active Low. I External Clock In. I External Clock In (negative polarity). 13 KS8695P M9999-051806 ...
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... Micrel, Inc. Pin Configuration May 2006 Figure 2. KS8695P Pin Mapping (Top View) 14 KS8695P M9999-051806 ...
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... KS8695P is especially suitable for cost-effective, power-sensitive applications. The KS8695P contains five 10/100 PHYs: four are for the local area network (LAN) and one is for the wide area network (WAN). Connected to the PHYs are five corresponding MAC units with an integrated Layer 2 managed switch. The combining of the switch and the analog PHYs make the KS8695P an extremely prudent solution for SOHO router applications, saving both board space and BOM costs ...
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... Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps • Supports full-/half-duplex operation on PHY interfaces • Fully compliant with IEEE 802.3 Ethernet standards • IEEE 802.3 full-duplex flow control and half-duplex backpressure collision flow control • Supports MDI/MDI-X auto-crossover May 2006 16 KS8695P M9999-051806 ...
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... High-speed UART interface up to 115kbps Other Features • Integrated PLL to generate CPU and system clocks • JTAG development interface for ICE connection • 19mm x 19mm 289-pin PBGA • 1.8V CMOS for core and 3.3V for I/O May 2006 17 KS8695P M9999-051806 ...
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... Micrel, Inc. Signal Description System Level Hardware Interfaces At the system level the KS8695P features the following interfaces: • Clock interface for crystal or external oscillator • JTAG development interface • One WAN Ethernet physical interface • Four LAN Ethernet physical interfaces • PHY LED drivers • ...
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... TEST2 Reset The KS8695P has a single reset input that can be driven by a system reset circuit or a simple power on reset circuit. The KS8695P also features a reset output (WRSTO) that can be used to reset other devices in the system. WRSTO can be configured as either an active high reset or an active low reset through a strap-in option on pin U17, as shown in Table 1. ...
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... Micrel, Inc. System Clock The clock to the KS8695P is supplied by either a 25MHz ±50ppm crystal oscillator oscillator is used, it must be connected to the XCLK1 input (pin E1) on the KS8695P crystal is used, it must be connected with a circuit similar to the one shown below. The 25MHz input clock is used by an internal PLL to generate the programmable SDOCLK. ...
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... The memory interface for the SDRAM and static memory has a special automatic address mapping feature. This allows the designer to connect address bit 0 on the memory to ADDR[0] on the KS8695P and address bit 1 on the memory to ADDR[1] on the memory, regardless of whether the designer is trying to achieve word, half word, or byte addressing. ...
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... Micrel, Inc. May 2006 Figure 8. SDRAM Interface Examples 22 KS8695P M9999-051806 ...
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... Micrel, Inc. KS8695P outputs ERWEN[3:0] as write strobes to byte wide, half-word wide, and word-wide memory port. The following figures show the most commonly implemented examples. May 2006 Figure 9. External I/O Interface Examples 23 KS8695P M9999-051806 ...
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... Micrel, Inc. May 2006 Figure 10. ERWEN[3:0] Interface Examples 24 KS8695P M9999-051806 ...
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... CPUCLKSEL=1 (factory reserved test signal). KS8695P chip reset. Active low input asserted for at least 256 system clock (40ns) cycles to reset the KS8695P. When in the reset state, all the output pins are tri- stated and all open drain signals are floating. Watchdog timer reset output. This signal is asserted for at least 200ms if RESETN is asserted or when the internal watchdog timer expires ...
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... TX/RX activity; ‘101’ = Full-duplex collision; ‘110’ = Link/Activity. LAN Port[4:1] LED indicator 1. Programmable via switch control 0 register bits [24:22]. ‘000’ = Speed; ‘001’ = Link; ‘010’ = Full/half duplex; ‘011’ = Collision; ‘100’ = TX/RX activity; ‘101’ = Full-duplex collision; ‘110’ = Link/Activity. 26 KS8695P M9999-051806 ...
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... General purpose I/O pin. General purpose I/O pin. PCI Reset. Active low. This signal is an input used to reset the KS8695P PCI logic. If the KS8695P is the host, use the RESETN signal to drive this input. If the KS8695P is a guest, use the system reset to drive this signal. ...
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... PCI address and data. PCI bus transactions consist of an address phase followed by one or more data phases. Address and data signals are multiplexed on the same pins. For a PCI write transaction, the source of the data is the KS8695P. For a PCI read transaction, the data source is the target. The KS8695P supports both read and write burst transactions ...
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... When it generates the PAR output, the KS8695P monitors for any reported parity error on PERRN. When the KS8695P is the bus master and a parity error is detected, the KS8695P sets error bits in the control status registers. It completes the current data burst transaction, and then stops the operation ...
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... During other cycles, the ADDR[21:0] is the byte address of the data transfer. For SDRAM and FLASH/ROM/SRAM, connect all address lines A1, etc. The memory controller automatically handles address line adjustments for the 8/16/32 bit accesses. For external I/O devices, the user needs to connect address lines for 8/16/32 bit accesses. 30 KS8695P M9999-051806 ...
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... ROM/SRAM/FLASH bank needs more access cycles than those defined in the corresponding control register. ROM/SRAM/FLASH Chip Select: Active low. The KS8695P can access up to two external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to map the CPU addresses into physical memory banks. ...
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... B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows: ‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved. (1) Description Factory test signal. Pull-down or direct connect to GND required. Factory test signal. No connect for normal operation. Factory test signal. No connect for normal operation. 32 KS8695P M9999-051806 ...
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... J12 J13 K12 K13 VDDA3 E11 VDD3.3 P E12 E13 F11 F12 F13 G12 G13 L12 L13 M10 M11 M12 M13 N10 N11 N12 N13 Note Power supply. May 2006 (1) Description 1.8V analog 1.8V digital core 3.3V analog 3.3V digital I KS8695P M9999-051806 ...
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... Micrel, Inc. Power and Ground Pins (continued) Pin Name I/O Type E3 AGND Gnd GND Gnd G10 G11 H8 H9 H10 H11 J8 J9 J10 J11 K8 K9 K10 K11 L8 L9 L10 L11 Note: 1. Gnd = Ground. May 2006 (1) Description Analog Ground. Ground. 34 KS8695P M9999-051806 ...
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... The AHB-PCI bridge configuration registers are also included in the SCRs. A subset of the AHB-PCI bridge configuration registers is also accessible to an external PCI host when the KS8695P is configured in PCI guest mode. Refer to the detailed Register Description document for additional information, including bit definitions. If you don’t have this document, contact your local Micrel Field Application Engineer or salesperson ...
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... J ( Air Flow................................29.86°C/W JA 1m/s ..........................................21.86°C/W 2m/s ..........................................21.54°C/W (θ Air Flow..................................8.34°C/W JC Min Typ 0.032 0.072 0.033 0.235 0.030 0.072 0.025 0.234 0.032 0.07 0.021 0.233 2.0 –10 2.4 KS8695P Max Units 0 µ µA M9999-051806 ...
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... Specification for packaged product only. May 2006 Condition 100Ω termination on the differential output 100Ω termination on the differential output Peak-to-peak 5MHz square wave 100Ω termination on the differential output 100Ω termination on the differential output 37 KS8695P Min Typ Max Units 0.95 1. ...
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... Symbol Parameter t Stable supply voltages to reset high SR t Configuration set-up time CS t Configuration hold time CH t Reset to strap-in pin output RC May 2006 tsr tch tcs trc Figure 11. Reset Timing Table 2. Reset Timing Parameters 38 KS8695P Min Typ Max Units M9999-051806 ...
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... RBiTACC Programmable bank i access time RBiTPA Programmable bank i page access time Table 3. Programmable Static Memory Timing Parameters Note: 1. "i" Refers to chip select parameters 0 and 1. May 2006 Figure 12. Static Memory Read Cycle Figure 13. Static Memory Write Cycle 39 KS8695P Registers 0x4010 0x4014 M9999-051806 ...
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... EBiTCOH Programmable bank i chip select hold time Note: 1. "i" Refers to chip select parameters May 2006 Figure 14. External I/O Read and Write Cycles Table 4. External I/O Memory Timing Parameters Table 5. Programmable External I/O Timing Parameters 40 KS8695P (1) (1) (1) Min Typ Max EBiTACS EBiTACS EBiTACS +0 ...
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... Micrel, Inc. (1) Symbol Parameter SDTRC Programmable SDRAM RAS to CAS latency SDCAS Programmable SDRAM CAS latency Note: 1. "i" Refers to chip select parameters 0 and 1. May 2006 Figure 15. DRAM Read Timing Figure 16. SDRAM Write Timing Table 6. SDRAM Timing Parameters 41 KS8695P Registers 0x4038 0x4038 M9999-051806 ...
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... Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully May 2006 289-Pin PBGA indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 42 KS8695P M9999-051806 ...