KS8695P-EVAL Micrel Inc, KS8695P-EVAL Datasheet
KS8695P-EVAL
Specifications of KS8695P-EVAL
Related parts for KS8695P-EVAL
KS8695P-EVAL Summary of contents
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... KS8695P General Description The CENTAUR KS8695P, Multi-Port PCI Gateway Solution, delivers a new level of networking integration, performance, and overall BOM cost savings, enabling original equipment manufacturers (OEMs) to provide customers with feature- rich, low-cost solutions for the residential gateway and small office environment. ...
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... KS8695P Features The CENTAUR KS8695P featuring XceleRouter technology is a single-chip, multi-port PCI "gateway-on-a-chip" with all the key components integrated for a high-performance and low-cost broadband gateway • ARM9 High-Performance CPU Core – ARM9 core at 166MHz – 8KB I-cache and 8KB D-cache – Memory management unit (MMU) for Linux and WinCE – ...
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... KS8695P Revision History Revision Date Summary of Changes 0.9 05/13/03 Created. 0.91 06/04/03 Corrected WRSTPLS sets WRSTO to active low when ‘1’, and active high when ‘0’. 0.92 06/10/03 Changed pin A1 to GND. Changed pin E3, H7, J7, K7 AGND. Changed Figure 5 WRSTPLS to pull up ...
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... KS8695P Contents System Level Applications ............................... Pin Description . ................................................ Pin Configuration ............................................ Functional Description .................................... Introduction ............................................... CPU Features ........................................... PCI to AHB Bridge Features ..................... Switch Engine ........................................... Advanced Memory Controller Features .... Direct Memory Access (DMA) Engines ..... Protocol Engine and XceleRouter™ Technology .....................................................................................................................16 Network Interface ...................................... Peripherals ................................................ Other Features .......................................... ...
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... SRAM 8/16/32 Bit 33MHz KS8695P Integrated Multi-Port 3 PCI PCI Masters Gateway Solution 10/100 10/100 10/100 10/100 TX/ Auto Auto Auto Auto MDI-X MDI-X MDI-X MDI-X Figure 1. KS8695P PCI Gateway System Options 5 802.11a/g/b PCI Multimedia USB 2.0 Web Printer Camera Micrel TV HDD M9999-081805 ...
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... KS8695P Pin Description Signal List Alphabetized by Name Pin Number Pin Name Type U4 ADDR0 T4 ADDR1 R3 ADDR10 P1 ADDR11 P2 ADDR12 N1 ADDR13 N2 ADDR14 N3 ADDR15 N4 ADDR16 M1 ADDR17 M2 ADDR18 M3 ADDR19 U3 ADDR2 P3 ADDR20/BA0 P4 ADDR2/BA1 T3 ADDR3 U2 ADDR4 U1 ADDR5 T1 ADDR6 T2 ADDR7 R1 ADDR8 R2 ADDR9 E3 AGND Gnd H7 AGND Gnd J7 AGND Gnd K7 AGND ...
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... KS8695P Pin Number Pin Name Type R12 DATA12 P12 DATA13 U11 DATA14 T11 DATA15 R11 DATA16 P11 DATA17 U10 DATA18 T10 DATA19 U14 DATA2 R10 DATA20 P10 DATA21 U9 DATA22 T9 DATA23 R9 DATA24 P9 DATA25 U8 DATA26 T8 DATA27 R8 DATA28 P8 DATA29 T14 DATA3 R7 DATA30 P7 DATA31 R14 ...
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... KS8695P Pin Number Pin Name Type R17 ERWEN3/ TICTESTENN P16 EWAITN D10 FRAMEN A1 GND Gnd G7 GND Gnd G8 GND Gnd G9 GND Gnd G10 GND Gnd G11 GND Gnd H8 GND Gnd H9 GND Gnd H10 GND Gnd H11 GND Gnd J8 GND Gnd J9 GND Gnd ...
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... KS8695P Pin Number Pin Name Type L16 GPIO15 H17 GPIO2/EINT2 H16 GPIO3/EINT3 H15 GPIO4/TOUT0 H14 GPIO5/TOUT1 J17 GPIO6 J16 GPIO7 J15 GPIO8 J14 GPIO9 D7 IDSEL A9 IRDYN F1 ISET B17 L1LED0 B16 L1LED1 C17 L2LED0 C16 L2LED1 D17 L3LED0 D16 L3LED1 E17 L4LED0 ...
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... KS8695P Pin Number Pin Name Type A15 PAD1 B13 PAD10 D13 PAD11 A12 PAD12 C12 PAD13 B12 PAD14 D12 PAD15 C9 PAD16 A8 PAD17 D9 PAD18 B8 PAD19 C15 PAD2 D8 PAD20 A7 PAD21 C7 PAD22 B7 PAD23 C6 PAD24 B6 PAD25 D6 PAD26 A5 PAD27 C5 PAD28 B5 PAD29 B15 PAD3 D5 PAD30 A4 PAD31 D15 ...
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... PCI Bus Request 2. Active Low. Input for Host Bridge Mode, Not Used in Guest Bridge Mode. I PCI Bus Request 3. Active Low. Input for Host Bridge Mode, Not Used in Guest Mode. I KS8695P Chip Reset. Active Low. O SDRAM Column Address Strobe. Active Low. O SDRAM Chip Select. Active Low Chip Select Pins for SDRAM. O SDRAM Chip Select ...
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... KS8695P Pin Number Pin Name Type N16 URXD N14 UTXD E7 VDD1.8 E8 VDD1.8 E9 VDD1.8 E10 VDD1.8 F7 VDD1.8 F8 VDD1.8 F9 VDD1.8 F10 VDD1.8 M7 VDD1.8 M8 VDD1.8 M9 VDD1.8 H12 VDD1.8 H13 VDD1.8 J12 VDD1.8 J13 VDD1.8 K12 VDD1.8 K13 VDD1.8 N7 VDD1.8 N8 VDD1.8 N9 VDD1.8 E11 VDD3.3 E12 VDD3 ...
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... KS8695P Pin Number Pin Name Type E5 VDDA1.8 E6 VDDA1.8 F5 VDDA1.8 F6 VDDA1.8 G5 VDDA1.8 G6 VDDA1.8 H5 VDDA1.8 H6 VDDA1.8 J5 VDDA1.8 J6 VDDA1.8 K5 VDDA3.3 K6 VDDA3.3 L5 VDDA3.3 L6 VDDA3.3 M5 VDDA3.3 M6 VDDA3.3 N5 VDDA3.3 N6 VDDA3.3 F2 WANFXSD G4 WANRXM G3 WANRXP G2 WANTXM G1 WANTXP E15 WLED0/ B0SIZE0 E14 WLED1/ B0SIZE1 U17 WRSTO E1 XCLK1 E2 XCLK2 Notes Power supply. ...
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... DATA30 DATA28 DATA24 DATA20 ADDR1 SDCASN SDQM1 SDICLK DATA27 DATA23 DATA19 ADDR0 SDWEN SDQM0 SDOCLK DATA26 DATA22 DATA18 LED Drivers Memory Interface GPIO Analog Figure 2. KS8695P Pin Mapping (Top View CBEN1 PAD12 PAD8 PAD5 PAD1 PAD0 RESETN PAD14 PAD10 PAD7 PAD3 ...
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... In guest bridge mode, all of the I/O registers are programmed by either the external host CPU on the PCI bus or the local ARM9 host processor through the AMBA bus. The KS8695P functions as a slave on the PCI bus with the on-chip PCI arbiter disabled. The KS8695PX can be configured by either the ARM9 CPU or the PCI host CPU. In both cases, the KS8695P memory subsystem is accessible from either the PCI host or the ARM9 CPU ...
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... KS8695P Switch Engine (continued) • Supports 802.1Q tag-based VLAN and port-based VLAN • Supports 8.2,1p-based priority, DiffServ priority, and post-based priority • Integrated address look-up engine, supports 1K absolute MAC addresses • Automatic address learning, address aging, and address migration • Broadcast storm protection • ...
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... LAN Ethernet PHY PHY LED Drivers Factory Test At the system level the KS8695P features the following interfaces: • Clock interface for crystal or external oscillator • JTAG development interface • One WAN Ethernet physical interface • Four LAN Ethernet physical interfaces • PHY LED drivers • ...
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... Chip Test Enable Reset The KS8695P has a single reset input that can be driven by a system reset circuit or a simple power on reset circuit. The KS8695P also features a reset output (WRSTO) that can be used to reset other devices in the system. WRSTO can be configured as either an active high reset or an active low reset through a strap-in option on pin U17, as shown in Table 1. ...
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... The clock to the KS8695P is supplied by either a 25MHz ±50ppm crystal oscillator oscillator is used, it must be connected to the XCLK1 input (pin E1) on the KS8695P crystal is used, it must be connected with a circuit similar to the one shown below. The 25MHz input clock is used by an internal PLL to generate the programmable SDOCLK. SDOCLK is the system clock and can be programmed from 25MHz to 125MHz using the system clock and bus control register at offset 0x0004 ...
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... The memory interface for the SDRAM and static memory has a special automatic address mapping feature. This allows the designer to connect address bit 0 on the memory to ADDR[0] on the KS8695P and address bit 1 on the memory to ADDR[1] on the memory, regardless of whether the designer is trying to achieve word, half word, or byte addressing. ...
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... KS8695P KS8695P outputs ERWEN[3:0] as write strobes to byte wide, half-word wide, and word-wide memory port. The following figures show the most commonly implemented examples August 2005 KS8695P 22 ADDR[21:0] 8 DATA[7:0] ECSN0 EROEN ERWEN0 KS8695P ADDR0 NC 21 ADDR[21:1] 16 DATA[15:0] ECSN0 EROEN ERWEN0 KS8695P NC ADDR0 ...
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... ERWEN2 ERWEN3 NC KS8695P DATA[15:0] ERWEN0 ERWEN1 NC NC ERWEN2 ERWEN3 NC KS8695P DATA[31:0] ERWEN0 NC ERWEN1 NC ERWEN2 ERWEN3 NC KS8695P DATA[15:0] DATA[31:0] ERWEN0 NC ERWEN1 ERWEN2 ERWEN3 NC DATA[31:16] Figure 10 ERWEN[3:0] Interface Examples 22 Byte Wide D[7:0] WE Half Word Wide D[15:0] WE Word Wide D[31:0] WE LSB Half Word Wide ...
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... CPUCLKSEL=1 (factory reserved test signal). KS8695P chip reset. Active low input asserted for at least 256 system clock (40ns) cycles to reset the KS8695P. When in the reset state, all the output pins are tri-stated and all open drain signals are floating. Watchdog timer reset output. This signal is asserted for at least 200ms if RESETN is asserted or when the internal watchdog timer expires ...
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... KS8695P LAN Ethernet Physical Interface Pins Pin Name I/O Type H1 LANTXP1 I J1 LANTXP2 K1 LANTXP3 L1 LANTXP4 H2 LANTXM1 I J2 LANTXM2 K2 LANTXM3 L2 LANTXM4 H3 LANRXP1 O J3 LANRXP2 K3 LANRXP3 L3 LANRXP4 H4 LANRXM1 O J4 LANRXM2 K4 LANRXM3 L4 LANRXM4 F1 ISET I F3 LANFXSD1 I PHY LED Drivers Pin Name I/O Type E15 ...
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... General purpose I/O pin. General purpose I/O pin. PCI Reset. Active low. This signal is an input used to reset the KS8695P PCI logic. If the KS8695P is the host, use the RESETN signal to drive this input. If the KS8695P is a guest, use the system reset to drive this signal. ...
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... PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In guest bridge mode, this signal is an output to indicate that the KS8695P is requesting to access the PCI bus as a PCI master. In guest bridge mode, this is basically the KS8695P’ ...
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... When it generates the PAR output, the KS8695P monitors for any reported parity error on PERRN. When the KS8695P is the bus master and a parity error is detected, the KS8695P sets error bits in the control status registers. It completes the current data burst transaction, and then stops the opera- tion ...
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... KS8695P General Purpose I/O Pins (continued) Pin Name I/O Type( D1 PCLKOUT3 O C1 PCLKOUT2 O B1 PCLKOUT1 O A2 PCLKOUT0 O B10 CLKRUNN I/O D2 MPCIACTN O D3 PBMS I Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O) Pin Name I/O Type T7 SDICLK I U7 SDOCLK O P4 ADDR21/BA1 O P3 ADDR20/BA0 O M3 ADDR[19] ...
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... External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695P also supports 8-bit and 16-bit data bus widths. SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695P supports up to two SDRAM banks. One SDCSN output is provided for each bank. ...
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... KS8695P Pin Name I/O Type T17 EROEN/ O/I WRSTPLS M17 ERWEN0/ O TESTACK N17 ERWEN1/ O TESTREQB P17 ERWEN2/ O TESTREQA R17 ERWEN3/ O TICTESTENN E15 WLED0/ O/I B0SIZE0 E14 WLED1/ O/I B0SIZE1 Factory Test Pins Pin Name I/O Type F7 TESTEN I M4 TEST1 I F4 TEST2 ...
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... KS8695P Power and Ground Pins Pin Name I/O Type E5 VDDA1 VDD1 E10 F10 H12 H13 J12 J13 K12 K13 VDDA3 E11 VDD3.3 P E12 E13 F11 F12 F13 G12 G13 L12 L13 M10 M11 M12 M13 N10 N11 N12 N13 Note Power supply. ...
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... KS8695P Pin Name I/O Type E3 AGND Gnd GND Gnd G10 G11 H8 H9 H10 H11 J8 J9 J10 J11 K8 K9 K10 K11 L8 L9 L10 L11 Note: 1. Gnd = Ground. August 2005 (1) Description Analog Ground. Ground. 32 Micrel M9999-081805 ...
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... The AHB-PCI bridge configuration registers are also included in the SCRs. A subset of the AHB-PCI bridge configuration registers is also accessible to an external PCI host when the KS8695P is configured in PCI guest mode. Refer to the detailed Register Description document for additional information, including bit definitions. If you don’t have this document, contact your local Micrel Field Application Engineer or salesperson ...
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... KS8695P Absolute Maximum Ratings Supply Voltage ( ......................................–0.5V to +2.4V DDA1.8 DD1 ......................................–0.5V to +4.0V DDA3.3 DD3.3 Input Voltage (all inputs) ...............................–0.5V to +4.0V Output Voltage (all outputs) ..........................–0.5V to +4.0V Lead Temperature (soldering, 10sec.) ....................... 270°C Pb (Lead) Free Temperature (soldering, 10sec) ........ 260°C Storage Temperature (T ) ........................ – ...
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... KS8695P Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage O V Output Voltage Imbalance IMB Rise/Fall Time r t Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Output Jitters 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer) ...
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... KS8695P Timing Diagrams For PCI timing, please refer to the PCI specification, version 2.1. Supply Voltages RESETN Strap-In Strap-In Pin Output Symbol Parameter t Stable supply voltages to reset high SR t Configuration set-up time CS t Configuration hold time CH t Reset to strap-in pin output ...
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... KS8695P SDOCLK RCSNi ADDR[21:0] EROEN ERWENi[3:0] DATA[31:0] SDOCLK RCSNi ADDR[21:0] EROEN ERWEN[3:0] DATA[31:0] (1) Symbol Parameter Programmable bank i access time RBiTACC RBiTPA Programmable bank i page access time Table 3. Programmable Static Memory Timing Parameters Note: 1. "i" Refers to chip select parameters 0 and 1. M9999-081805 RBiTACC ...
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... KS8695P SDOCLK ECSN[i] ADDR[21:0] EROEN ERWEN[3:0] EWAITN DATA[31:0] Symbol Parameter T Valid address to CS setup time cta +0 valid to CS setup time cos +0.6 T Valid read data to OE setup time dsu T WE valid to CS setup time cws +0.6 T Write data to CS hold time ...
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... KS8695P SDOCLK (1) SDCSNi ADDR[21:0] SDRASN SDCASN SDWEN SDQM[3:0] DATA[31:0] SDOCLK ��� SDCSNi ADDR[21:0] SDRASN SDCASN SDWEN SDQM[3:0] DATA[31:0] Symbol Parameter Programmable SDRAM RAS to CAS latency SDTRC Programmable SDRAM CAS latency SDCAS Note: 1. "i" refers to chip select parameters 0,1. M9999-081805 ...
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... KS8695P Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...