AD9510-VCO/PCB Analog Devices Inc, AD9510-VCO/PCB Datasheet - Page 20

• Manufacturer Part Number: AD9510-VCO/PCB
• Description: BOARD EVAL CLOCK DISTR 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9510-VCO/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9510/PCB
Divider, Phase, and Duty Cycle Settings Window
The divider, phase, and duty cycle settings window for each of the eight inputs is opened by left-clicking on the divider block for the
appropriate input. The divider 2 settings window is displayed in Figure 26. The divider settings windows for outputs 1 to 7 are identical.
The three major controls in the divider settings window are the divider, phase, and duty cycle settings.
BYPASS
(POWER DOWN)
DIVIDER RATIO
PHASE OFFSET
START LOW/HIGH
SYNC CONTROL BITS
DUTY CYCLE
Figure 26. Divider 2 Settings Window
The divider ratio is the core of the divider block. This value specifies your output frequency. The formula is
f
= f
/M
out
in
where M is the divider ratio.
Next, a duty cycle needs to be determined. The duty cycle is specified by the ratio of high clock cycles to low clock cycles. High clock
cycles are the number of master clock cycles that the output is high. Low clock cycles are the number of master clock cycles that the
output is low. The evaluation software programs the correct number of cycles depending on the duty cycle chosen. When programming
the part manually, remember that the number of high (or low) clock cycles is the value programmed plus one.
The phase offset allows you to shift the phase of the output signal by an integer number of master clock cycles. The maximum value of the
phase offset is 15. Related to the phase-offset setting is the start high/low setting, which allows you to specify if the outputs start in a high
state or a low state after a sync event. When coupled with the phase-offset setting, it allows for 32 phase-offset states. However, the
number of unique phase-offset states is limited by the divide ratio, because the phase offset is controlled by the master clock frequency. In
general, the number of unique phase offsets is equal to the divider ratio. The actual phase step, in degrees, is given by 360º/(divider ratio).
The bypass (power down) and miscellaneous control bits give you control over the sync and power down settings of the divider. When
both sync bits are set, the output is frozen in a high or low state (the complimentary out is frozen in the opposite). The choice of high or
low is dictated by the start high or start low setting. Please refer to the AD9510 data sheet for more information on soft sync and ignoring
chip-level sync.
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