EVAL-AD5381EB Analog Devices Inc, EVAL-AD5381EB Datasheet - Page 3

BOARD EVAL FOR AD5381

EVAL-AD5381EB

Manufacturer Part Number
EVAL-AD5381EB
Description
BOARD EVAL FOR AD5381
Manufacturer
Analog Devices Inc
Datasheets

Specifications of EVAL-AD5381EB

Rohs Status
RoHS non-compliant
Number Of Dac's
40
Number Of Bits
12
Outputs And Type
40, Single Ended
Sampling Rate (per Second)
167k
Data Interface
DSP, I²C, MICROWIRE™, Parallel, QSPI™, SPI™
Settling Time
6µs
Dac Type
Voltage
Voltage Supply Source
Single
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD5381
GENERAL DESCRIPTION
The AD5381 is a complete, single-supply, 40-channel, 12-bit
DAC available in a 100-lead LQFP package. All 40 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5381 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference, an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring, and an output amplifier boost mode,
which allows optimization of the amplifier slew rate. The
AD5381 contains a double-buffered parallel interface featuring
20 ns WR pulse width, an SPI-/QSPI-/MICROWIRE-/DSP-
compatible serial interface with interface speeds in excess of
30 MHz, and an I
400 kHz data transfer rate.
Table 1. Other Low Voltage Single-Supply DACs in Product Family
Model
AD5380BST-5
AD5380BST-3
AD5384BBC-5
AD5384BBC-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
AD5390BST-5
AD5390BCP-5
AD5390BST-3
AD5390BCP-3
AD5391BST-5
AD5391BCP-5
AD5391BST-3
AD5391BCP-3
AD5392BST-5
AD5392BCP-5
AD5392BST-3
AD5392BCP-3
Table 2. 40-Channel, Bipolar Voltage Output DAC
Model
AD5379ABC
AD5378ABC
Resolution
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
Resolution
14 Bits
14 Bits
2
C-compatible interface that supports a
Analog Supplies
±11.4 V to ±16.5 V
±11.4 V to ±16.5 V
AVDD Range
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
Output Channels
40
32
Output Channels
40
40
40
40
32
32
32
32
16
16
16
16
16
16
16
16
8
8
8
8
Rev. B | Page 3 of 40
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated independ-
ently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC chan-
nel. Power consumption is typically 0.25 mA/channel with
boost mode disabled.
Linearity Error
(LSB)
±4
±4
±4
±4
±4
±4
±1
±1
±3
±3
±4
±4
±1
±1
±1
±1
±3
±3
±4
±4
Linearity
Error
±3
±3
Package
108-Lead CSPBGA
108-Lead CSPBGA
Package
Description
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
Package Option
ST-100
ST-100
BC-80
BC-80
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
Package Option
BC-108
BC-108
AD5381

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