MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 88

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PowerQUICC II Register Programming
Reg.
OR1
OR2
OR4
OR5
OR3
Table 6-7. Memory Controller Initialization For 100MHz—E
Reg.
OR0
OR1
OR2
BR1
BR2
BR4
BR5
BR3
BR0
BR1
BR2
Table 6-6. Memory Controller Initialization For 100MHz—Flash as Boot Device
BCSR
SDRAM
MT48LC4M32B2
MICRON
E
AT28HC64B-70JC
Atmel
PM5384 - ATM UNI
PCI Interrupt Controller
E
AT28HC64B-70JC
Atmel
BCSR
SDRAM
MT48LC8M16A2
MICRON
2
2
PROM
PROM
Device Type
Device Type
by
by
by
by
PPC
PPC
PPC
PPC
PPC
PPC
PPC
PPC
Bus
Bus
MPC8272ADS User Guide
FE002EC0
FE002EC0
FFFF8E56
FFFF8010
C2000801
FFFF8866
FFFF8010
FFF00801
FFFF8866
FFFF8010
Init Value
04501801
00000041
04600801
04731801
Init Value
04501801
00000041
[hex]
[hex]
32 KByte block size, CS output half a clock after
32 KByte block size, CS output half a clock after
Base at 04500000, 32 bit port size, no parity,
GPCM
32 KByte block size, all types access, 1 w.s.
Base at 0, 64 bit port size, no parity, SDRAM
machine 1
32MByte block size, 4 banks per device, row starts
at A7, 12 row lines, internal bank interleaving
allowed, normal AACK operation
Base at C2000000, 8 bit port size, write protect
disabled, no parity, GPCM
address, all types access, 6 w.s., Timing relax
Base at 04600000, 8 bit port size, no parity, GPCM
on PPC bus.
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
Base at 04730000, 32 bit port size, no parity,
GPCM on PPC bus.
32 KByte block size, all types access, 1 w.s.
Base at FFFFE000, 8 bit port size, write protect
disabled, no parity, GPCM
address, all types access, 6 w.s., Timing relax
Base at 04500000, 32 bit port size, no parity,
GPCM
32 KByte block size, all types access, 1 w.s.
Base at 0, 64 bit port size, no parity, SDRAM
machine 1
32MByte block size, 4 banks per device, row starts
at A7, 12 row lines, internal bank interleaving
allowed, normal AACK operation
2
PROM as Boot Device
Description
Description