MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 48

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset and Reset Configuration
can be taken from the E2PROM/BCSR in case the Flash has been tampered with. The
selection between the BCSR, FLASH and the E2PROM as the source of the default
configuration word is determined by a dedicated dip-switch and a jumper.
During hard reset sequence, the configuration master
BCSR) memory at addresses 0, 8, 0x18, 0x20,... a byte each time, to assemble the 32 bit
configuration word. A total of 64 bytes of data is read from D(0:7) to acquire 8 full
configuration words for system that may have up to 8 MPC8272 chips.
The configuration word for a single
the E
there are no additional MPC8272 on the MPC8272ADS. The default configuration word is
shown in Table 5-1 for the FLASH and in Table 5-2 for the E
configuration is 256 Bytes long and should start at address 0x100.
The two possible configuration words are the following:
ERB
EXMC
CDIS
EBM
BPS
CIP
ISPS
.
• FLASH/BCSR is the boot device. CS0 is assigned to the FLASH and CS4 is
• E
1
2
In general, The
Although the
Field
2
the
word is influential.
PROM or as default in the BCSR, while the other seven words are not initialized, as
assigned to the E
to the FLASH.
2
MPC8272
PROM is the boot device. CS0 is assigned to the E
Table 5-1. BCSR/FLASH Hard Reset Configuration Word
MPC8272
Data
Bus
Bits
MPC8272
4:5
0
1
2
3
6
7
residing on the MPC8272ADS.
2
Value
Prog
[Bin]
as configuration master reads 8 configuration words, only the 1’st configuration
PROM.
’0’
’0’
’0’
’0’
11
’0’
‘0’
for which RSTCONF is asserted along with PORST asserted or in particular,
Internal Arbitration Selected.
Internal Memory Controller. CS0 active at
system boot.
Core Enabled.
‘0’ - Single PowerQUICC II Mode
32 Bit Boot Port Size
Sets Core Initial Prefix MSR[IP]=1, so that
system exception table is placed at address
0xFFF00100 regardless of FLASH memory
size
64-bit internal space for external master
accesses. In fact don’t care on this board since
external master is not supported.
MPC8272ADS User Guide
2
MPC8272 is stored in the Flash memory SIMM, in
Implication
1
reads the Flash (or E
2
PROM and CS4 is assigned
2
PROM. PCI module
Offset In
Flash
[Hex]
0
2
PROM or
Value
[Hex]
0C