MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 47

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.1.3.2
To allow runtime hard-reset, when the COP controller is disconnected from the
MPC8272ADS, and to support resident debuggers, manual hard is facilitated. Depressing
both soft reset (SW7) and ABORT (SW6) buttons assert
MPC8272, generating a hard reset sequence.
Because the HRESET line may be driven internally by the MPC8272, it must be driven to
the MPC8272 with an open-drain gate. If off-board hardware connected to the
MPC8272ADS is to drive HRESET line, it should do so with an open-drain gate, to avoid
contention over this line.
When hard reset is generated, the MPC8272 is reset in a destructive manner, that is, the hard
reset configuration is re-sampled and all registers (except for the PLL’s) are reset, including
memory controller registers. This reset causes loss of dynamic memory contents.
To save on board’s real-estate, this button is not a dedicated one, but is shared with the
soft-reset button and the ABORT button. When both are depressed, hard reset is generated.
5.1.3.3
The MPC8272 has internal sources that generate hard reset. Among these sources are the
following:
The MPC8272 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset
source is identified. A hard reset sequence is followed by a soft reset sequence.
5.1.3.4
When hard reset is applied to the MPC8272 (externally as well as internally), it samples the
hard reset configuration word. This configuration may be taken from an internal default, in
case RSTCONF is negated during HRESET asserted or taken from the Flash
/E2PROM/BCSR (MS 8 bits of the data bus) (in general, from any device residing on CS0)
in case RSTCONF signal is asserted along with HRESET. The default configuration word
• Loss of lock reset. When one of the PLLs (core, CPM), is out of lock, hard-reset is
• Check-stop reset. When the core enters a check-stop state from some reason, a hard
• Bus monitor reset. When the bus monitor is enabled and a bus cycle is not
• S/W Watch Dog Reset. When the S/W watch-dog is enabled, and application
• COP/JTAG Reset (Internal). Hard reset may be forced by driving the HRESET line
generated.
reset may be generated, depending on the CSRE bit in the RMR.
terminated, hard-reset is generated.
software fails to perform its reset routine, it generates hard reset.
using the external pin’s scan chain. Not useful for run time.
Manual Hard Reset
Internal Sources Hard Reset
Hard Reset Configuration
Chapter 5. Module Design
s
Reset and Reset Configuration
the HRESET pin of the