MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 75

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BIT
5.11.4 BCSR3 Board Control - Status Register 3
BCSR3 is a control register which is accessed at offset 0xC from the BCSR base address.
Its a read- write register which may be read or written at any time
are described in Table 5-16
0
1
2
3
4
5
6
1
Provided that BCSR is not disabled.
ATM_SINGLE_PH
USB_HI_SPEED
FETH2_RST
MNEMONIC
FETHIEN2
USBVCC0
USB_EN
ATM16
Y
TOOLREV(0:3) [hex]
Table 5-15. External Tool Revision Encoding
USB Port Enable. When asserted (low) the USB chip connected to SCC4
is enabled for transmission and reception. When negated, the USB
transceiver is in standby mode and its associated buffers
mode, freeing all its i/f signals for off-board use via the expansion
connectors.
USB Hi Speed. When asserted (low) the USB chip connected to SCC4 is
set for hi speed (12 Mbps) transmission and reception. When negated, the
USB transceiver is set to low speed (1.5 Mbps) transmission and reception
USB Port VCC EN. When asserted (high), 5V power is applied to the USB
Bus. When negated, power to the USB port is disconnected.
Fast Ethernet Port 2 Initial Enable. When asserted (low) the DM9161’s
MII port, residing on FCC3, is enabled after Power-Up or after FETH_RST
is negated. When negated (high), the DM9161’s MII port is isolated after
Power-Up or after FETH_RST is negated and all i/f signals are tri-stated.
After initial value has been set, this signal has no influence over the
DM9161 and MII isolation may be controlled via MDIO 0.10 bit.
Fast Ethernet port 2 Reset. When active (low) the DM9161 is reset. This
line is also driven by HRESET signal of the PowerQUICC II. Since MDDIS
pin of the DM9161 is driven low with this application, the negation of this
signal causes all the H/W configuration bits to be sampled for initial values
and device control is moved to the MDIO channel, which is the control path
of the MII port.
ATM 16 bit UTOPIA. When asserted (low) the UTOPIA is set for 16 bit.
When negated (high), the UTOPIA is set for 8 bit.
ATM SINGLE PHY. When asserted (low) the UTOPIA is set to Multi PHY.
When negated (high), the UTOPIA is set for Single PHY.
3 - F
0
1
2
Table 5-16. BCSR3 Description
Chapter 5. Module Design
Function
External Tool Revision
Board Control and Status Register - BCSR
ENGINEERING
Reserved
PILOT
A
1
. BCSR3s’ various fields
1
are in tri-state
PON
DEF
1
0
0
1
1
1
1
ATT.
R/W
R/W
R/W
R/W
R/W
R/W
R/W