MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 57

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 34
Figure 35
Figure 36
Freescale Semiconductor
At recommended operating conditions (see
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
inputs and t
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
Table 50. JTAG AC Timing Specifications (Independent of SYSCLK)
External Clock
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
TRST
JTAG
Parameter
Output
Figure 34. AC Test Load for the JTAG Interface
JTG
Figure 35. JTAG Clock Input Timing Diagram
Table
VM
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
JTKHKL
Boundary-scan data
Figure 36. TRST Timing Diagram
3).
VM
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
TCLK
JTDXKH
t
Z
TCLK
JTG
0
= 50 Ω
.
VM
.
symbolizes JTAG timing (JT) with respect to the time data input signals
t
TRST
TDO
Symbol
(first two letters of functional block)(signal)(state)(reference)(state)
VM
t
t
for outputs. For example, t
JTKLDZ
JTKLOZ
2
R
VM
L
= 50 Ω
TCLK
t
JTGR
Min
3
3
to the midpoint of the signal in question.
OV
JTDVKH
DD
1
t
JTGF
Max
/2
(continued)
19
9
symbolizes JTAG device
JTG
clock reference (K)
Unit
Figure
ns
34).
Notes
for
5
JTAG
57