C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 49
![BOARD PROTOTYPING W/C8051F020](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F020-TB
Manufacturer Part Number
C8051F020-TB
Description
BOARD PROTOTYPING W/C8051F020
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F020-TB
Contents
Board
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F020
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits7-3:
Bits2-0:
AD0SC4
R/W
Bit7
AD0SC4-0: ADC0 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers
to the 5-bit value held in AD0SC4-0, and CLK
Table 5.1 on page 58 for SAR clock setting requirements.
AD0SC
AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F020/1)
AD0SC3
R/W
Bit6
=
---------------------- - 1
CLK
SYSCLK
AD0SC2
R/W
Bit5
SAR0
–
AD0SC1
R/W
Bit4
AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000
R/W
Bit3
Rev. 1.4
SAR0
refers to the desired ADC0 SAR clock. See
R/W
Bit2
R/W
Bit1
C8051F020/1
R/W
Bit0
SFR Address:
Reset Value
0xBC
49
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