C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 17
C8051F020-TB
Manufacturer Part Number
C8051F020-TB
Description
BOARD PROTOTYPING W/C8051F020
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F020-TB
Contents
Board
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F020
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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1.
The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins
(C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for
specific product feature selection.
•
•
•
•
•
•
•
•
•
•
•
•
With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F020/1/2/3 devices are truly stand-
alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user
firmware. The FLASH memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also
allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging
using the production MCU installed in the final application. This debug system supports inspection and modification
of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and
digital peripherals are fully functional while debugging using JTAG.
Each MCU is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-45° C to +85° C). The
Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F020/2 are available in a 100-pin
TQFP package (see block diagrams in Figure 1.1 and Figure 1.3). The C8051F021/3 are available in a 64-pin TQFP
package (see block diagrams in Figure 1.2 and Figure 1.4).
C8051F020
C8051F021
C8051F022
C8051F023
High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 12-bit (C8051F020/1) or 10-bit (C8051F022/3) 100 ksps 8-channel ADC with PGA and analog multiplexer
True 8-bit ADC 500 ksps 8-channel ADC with PGA and analog multiplexer
Two 12-bit DACs with programmable update scheduling
64k bytes of in-system programmable FLASH memory
4352 (4096 + 256) bytes of on-chip RAM
External Data Memory Interface with 64k byte address space
SPI, SMBus/I
Five general purpose 16-bit Timers
Programmable Counter/Timer Array with five capture/compare modules
On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor
SYSTEM OVERVIEW
25
25
25
25
2
C, and (2) UART serial interfaces implemented in hardware
64k 4352
64k 4352
64k 4352
64k 4352
Table 1.1. Product Selection Guide
2
2
2
2
5
5
5
5
Rev. 1.4
64
32
64
32
8
8
-
-
8
8
-
-
8
8
8
8
C8051F020/1/2/3
12
12
12
12
2
2
2
2
2 100TQFP
2
2 100TQFP
2
64TQFP
64TQFP
17
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