C8051F300-TB Silicon Laboratories Inc, C8051F300-TB Datasheet - Page 98
C8051F300-TB
Manufacturer Part Number
C8051F300-TB
Description
BOARD PROTOTYPING W/C8051F300
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F300-TB
Contents
Board
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F300
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F300/1/2/3/4/5
98
Bit7:
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
Bits7–5: UNUSED. Read = 000b, Write = don't care.
Bit4:
Bit3:
Bit2:
Bits1–0: IFCN1-0: Internal Oscillator Frequency Control Bits.
R/W
R/W
Bit7
Bit7
—
—
UNUSED. Read = 0. Write = don’t care.
This register calibrates the internal oscillator period. The reset value for OSCICL defines the
internal oscillator base frequency. On C8051F300/1 devices, the reset value is factory cali-
brated to generate an internal oscillator frequency of 24.5 MHz.
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
CLKSL: System Clock Source Select Bit.
0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits.
1: SYSCLK derived from the External Oscillator circuit.
IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
SFR Definition 11.1.
R/W
R/W
Bit6
Bit6
SFR Definition 11.2.
—
R/W
R/W
Bit5
Bit5
—
IFRDY
R/W
Bit4
Bit4
R
OSCICL: Internal Oscillator Calibration
OSCICN: Internal Oscillator Control
CLKSL
Rev. 2.9
R/W
Bit3
R/W
Bit3
IOSCEN
R/W
Bit2
R/W
Bit2
IFCN1
R/W
Bit1
R/W
Bit1
IFCN0
R/W
Bit0
R/W
Bit0
SFR Address:
SFR Address:
00010100
Reset Value
Reset Value
Variable
0xB2
0xB3
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