AT91RM9200-EK Atmel, AT91RM9200-EK Datasheet - Page 30

• Manufacturer Part Number: AT91RM9200-EK
• Description: DEVEL KIT
• Manufacturer: Atmel
• Series: ARM®, Thumb®r
• Type: MCUr

Specifications of AT91RM9200-EK

• Contents: Development Board, AC adapter, Cables and Software
• Processor To Be Evaluated: AT91RM9200
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• For Use With/related Products: ARM920T
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2427672

10.14 Serial Peripheral Interface
10.15 Two-wire Interface
10.16 USART
30
AT91RM9200
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operation
• MII or RMII interface to the physical layer
• Register interface to address, status and control registers
• DMA interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Supports promiscuous mode where all valid frames are copied to memory
• Supports physical layer management through MDIO interface
• Supports communication with serial external devices
• Master or slave serial peripheral bus interface
• Connection to PDC channel optimizes data transfers
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential Read/Write operations
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– Four chip selects with external decoder support allow communication with up to 15
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– One channel for the receiver, one channel for the transmitter
– Next buffer support
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
peripherals
Sensors
and data per chip select
1768MS–ATARM–09-Jul-09