AT91RM9200-EK Atmel, AT91RM9200-EK Datasheet - Page 19

• Manufacturer Part Number: AT91RM9200-EK
• Description: DEVEL KIT
• Manufacturer: Atmel
• Series: ARM®, Thumb®r
• Type: MCUr

Specifications of AT91RM9200-EK

• Contents: Development Board, AC adapter, Cables and Software
• Processor To Be Evaluated: AT91RM9200
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• For Use With/related Products: ARM920T
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2427672

9. System Peripherals
9.1
9.2
9.3
1768MS–ATARM–09-Jul-09
Reset Controller
Advanced Interrupt Controller
Power Management Controller
A complete memory map is shown in
• Two reset input lines (NRST and NTRST) providing, respectively:
• Initialization of the User Interface registers (defined in the user interface of each peripheral)
• Initialization of the embedded ICE TAP controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
• 8-level Priority Controller
• Vectoring
• Protect Mode
• General Interrupt Mask
• Optimizes the power consumption of the whole system
• Embeds and controls:
• Provides:
and:
– Sample the signals needed at bootup
– Compel the processor to fetch the next instruction at address zero
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU…)
– Source 2 to Source 31 control thirty embedded peripheral interrupts or external
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
– Easy debugging by preventing automatic operations
– Provides processor synchronization on events without triggering an interrupt
– One Main Oscillator and One Slow Clock Oscillator (32.768Hz)
– Two Phase Locked Loops (PLLs) and Dividers
– Clock Prescalers
– the Processor Clock PCK
interrupts
External Sources
Figure 8-1 on page
17.
AT91RM9200
19