AT91RM9200-EK Atmel, AT91RM9200-EK Datasheet - Page 14

• Manufacturer Part Number: AT91RM9200-EK
• Description: DEVEL KIT
• Manufacturer: Atmel
• Series: ARM®, Thumb®r
• Type: MCUr

Specifications of AT91RM9200-EK

• Contents: Development Board, AC adapter, Cables and Software
• Processor To Be Evaluated: AT91RM9200
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• For Use With/related Products: ARM920T
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2427672

6.4
7. Processor and Architecture
7.1
7.2
14
PIO Controller A, B, C and D Lines
ARM920T Processor
Debug and Test
AT91RM9200
All the I/O lines PA0 to PA31, PB0 to PB29, PC0 to PC31 and PD0 to PD27 integrate a program-
mable pull-up resistor of 15 kOhm typical. Programming of this pull-up resistor is performed
independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that must be enabled as peripherals at
reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing
tables.
8-, 16-, 32-bit Data Bus for Instructions and Data
• ARM9TDMI
• Two instruction sets
• 5-Stage Pipeline Architecture:
• 16-Kbyte Data Cache, 16-Kbyte Instruction Cache
• Write Buffer
• Standard ARMv4 Memory Management Unit (MMU)
• Integrated EmbeddedICE
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 64-way Associative Cache
– 8 words per line
– Write-though and write-back operation
– Pseudo-random or Round-robin replacement
– Low-power CAM RAM implementation
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain
– Access permission for sections
– Access permission for large pages and small pages can be specified separately for
– 16 embedded domains
– 64 Entry Instruction TLB and 64 Entry Data TLB
each quarter of the pages
™
-based on ARM Architecture v4T
1768MS–ATARM–09-Jul-09