MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 125

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
The following documents are required for a complete description of the chip and are needed to design properly with the part.
7
This table provides a revision history for this hardware specification.
Freescale Semiconductor
Revision
2.
3.
4.
5.
6.
7.
•
•
4
3
2
1
0
Dimensions and tolerances per ASME Y14.5M-1994.
Maximum solder ball diameter measured parallel to datum A
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
Capacitors may not be present on all devices
Caution must be taken not to short exposed metal capacitor pads on package top.
All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
MPC8536E PowerQUICC III Integrated Processor Reference Manual (document number: MPC8536ERM)
e500 PowerPC Core Reference Manual (document number: E500CORERM)
Product Documentation
Document Revision History
06/2011
11/2010
09/2009
09/2009
08/2009
Date
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Note:
Note: Updated
• In
• Updated
• In
• In
• Updated
• Updated
• In
• Added Note 6 regarding USB n _DIR pin to
• In
• In
• In
• In
• In
• Initial public release.
(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required...”
In addition, updated footnote 26 and added footnote 29 to PCI1_AD.
MDIO/MDC.
UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.”
LSTSEF to LSTSE for Note 4.
Section 1, “Pin Assignments and Reset
Table
Section 4.3, “Part Numbering,”
Table
Table
Table
Table
Table
Table
FC-PBGA,” and its notes.
1, “Pinout Listing,” updated the power supply for TSEC3 pins to TVDD.
1, “Pinout Listing,” added the following note: “For systems that boot from Local Bus
44, “MII Management DC Electrical Characteristics,” changed the Voh/Vol values for
64, “I2C AC Electrical Specifications,” updated footnote 2.
82,
40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and
5, ”Power Dissipation 5,” changed an “—”’ to “0.”
Table
Table 21
Figure
Table
Figure
Table 85. Document Revision History
56, “eSDHC AC Timing Specifications.”
25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.”
83,
81, “Mechanical Dimensions and Bottom Surface Nomenclature of the
Table
84, added the Revision Level A for Rev 1.2
added an extra bin (1250/500/667) to support DDR3.
Substantive Change(s)
States,”updated the first sentence of the note to say, “The
Table
47, “USB General Timing Parameters6.”
Product Documentation
125