MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 119

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Notes:
COP Connector
order to fully control the processor as shown here.
improved signal integrity.
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to
position B.
Physical Pinout
13
15
11
1
1
3
5
7
9
Board Sources
No pin
KEY
From Target
10
12
16
4
6
8
2
(if any)
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
14
5
13
15
10
12
16
SRESET
11
HRESET
4
6
8
9
1
3
7
2
3
3
COP_CHKSTP_IN
COP_CHKSTP_OUT
COP_VDD_SENSE
COP_TMS
COP_TDO
COP_TDI
COP_TCK
COP_SRESET
COP_TRST
COP_HRESET
NC
NC
Figure 78. JTAG Interface Connection
NC
4
2
5
10 kΩ
10 Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Hardware Design Considerations
OV
DD
SRESET
HRESET
TRST
CKSTP_OUT
CKSTP_IN
TMS
TDO
TDI
TCK
1
1
6
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