XE8000EV110 Semtech, XE8000EV110 Datasheet - Page 36

• Manufacturer Part Number: XE8000EV110
• Description: EVAL BOARD FOR XE8802AMI035LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV110

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC02MI035
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.3.14
Address
h0068
h0069
h006A
h006B
h006C
h006D
Table 4-17. SPI register description.
4.3.15
Address
h0070
Table 4-18. LCD voltage generator register.
4.3.16
Address
h0072
h0073
Table 4-19. Low power comparator registers
4.3.17
Address
h007C
Table 4-20. VMULT register.
4.3.18
Address
h007E
h007F
Table 4-21. Voltage level detector register description
4.3.19
The 1024 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables
stored in the RAM should be initialised before use since they can have any value at circuit start up.
© Semtech 2006
RegSpiDataOut
RegSpiControl
RegVmultCfg0
RegSpiDataIn
RegVgenCfg0
RegCmpdStat
RegSpiStatus
RegSpiPullup
RegCmpdCtrl
RegVldStat
RegVldCtrl
RegSpiDir
Name
Name
Name
Name
Name
SPI registers (h0068-h006F)
LCD voltage generator registers (h0070)
Comparator registers (h0072-h0073)
Voltage multiplier (h007C)
Voltage Level Detector registers (h007E-h007F)
RAM (h0080-h047F)
ClearCounter
c1 r0
r0
r0
r0
r0
r0
r0
r0
7
7
7
7
7
IrqOnRising[2:0]
rw,000,glob
NotSlaveSelect
rw,1,glob
r0
r0
r0
r0
r0
r0
r0
6
6
6
CmpdStat[3:0]
6
6
rca,0000,glob
SpiMaster
rw,1,glob
VgenClkSel[1:0]
r0
r0
r0
r0
r0
r0
5
5
5
5
5
XE8802 Sensing Machine Data Acquisition MCU
rw,10,glob
SpiEnable
rw,0,glob
rw,00000000,glob
SpiDataOut[7:0]
r,00000000,glob
r0
r0
r0
r0
r0
r0
4
SpiDataIn[7:0]
4
4
4
4
4-9
ClockPhase
VldRange
with ZoomingADC™ and LCD driver
rw,1,glob
rw,1,glob
rw,0,glob
VgenOff
r0
r0
r0
3
3
3
3
3
rw,0000,glob
EnIrqCh[3:0]
SpiOverflow
ClockPolarity
VgenMode
r c1,0,glob
VldResult
rw,0,glob
rw,0,glob
rw,0,glob
r,0,glob
Enable
2
2
2
2
2
rw,1111,pconf
rw,0000,pconf
CmpdOut[3:0]
SpiPullup[3:0]
r,0000,glob
SpiDir[3:0]
VldTune[2:0]
rw,000,glob
VgenStdb
SpiRxFull
rw,0,glob
VldValid
r,0,glob
r,0,glob
1
1
1
1
1
BaudRate[1:0]
rw,00,glob
rw,00,glob
Fin[1:0]
VgenRefEn
r w1,1,glob
SpiTxEmpty
rw,0,glob
rw,0,glob
rw,0,glob
Enable
VldEn
0
0
0
0
0
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