ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 61

• Manufacturer Part Number: ADZS-BF527-EZLITE
• Description: BOARD EVAL ADSP-BF527
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF527-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Evaluation Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Silicon Core Number: ADSP-BF527
• Silicon Family Name: Blackfin
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Preliminary Technical Data
Table 54. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
1
2
Table 55. 10/100 Ethernet MAC Controller Timing: MII Station Management
1
Parameter
t
t
t
t
Parameter
t
t
t
t
MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to
The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
ECOLH
ECOLL
ECRSH
ECRSL
MDIOS
MDCIH
MDCOV
MDCOH
both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
of the system clock SCLK. MDIO is a bidirectional data line.
ERx_CLK
ERxD3-0
ERxDV
ERxER
1, 2
1
ETxD3-0
ETxEN
MII TxCLK
COL Pulse Width High
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
t
ERXCLKIS
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Figure 35. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
t
ETXCLKOH
t
ERXCLKIH
t
ETXCLKW
t
ETXCLKOV
Rev. PrG | Page 61 of 80 | February 2009
t
ERXCLKW
t
ETXCLK
t
ERXCLK
Min
11.5
11.5
t
t
t
t
t
t
25
–1
ETxCLK
ERxCLK
ETxCLK
ERxCLK
ETxCLK
ETxCLK
ADSP-BF522/524/526
V
1.8 V
DDEXT
Min
ADSP-BF522/523/524/525/526/527
V
x 1.5
x 1.5
x 1.5
x 1.5
x 1.5
x 1.5
Max
DDEXT
=
= 1.8 V
Min
11.5
11.5
25
2.5/3.3 V
–1
V
DDEXT
Max
Max
=
Min
t
t
t
t
t
t
10
10
25
–1
ETxCLK
ERxCLK
ETxCLK
ERxCLK
ETxCLK
ETxCLK
ADSP-BF523/525/527
V
DDEXT
1.8 V
Min
V
DDEXT
x 1.5
x 1.5
x 1.5
x 1.5
x 1.5
x 1.5
Max
=
= 2.5/3.3 V
Min
10
10
25
–1
2.5/3.3 V
V
DDEXT
Max
Max Unit
=
Unit
ns
ns
ns
ns
ns
ns
ns
ns