ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 38

• Manufacturer Part Number: ADZS-BF527-EZLITE
• Description: BOARD EVAL ADSP-BF527
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF527-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Evaluation Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Silicon Core Number: ADSP-BF527
• Silicon Family Name: Blackfin
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF522/523/524/525/526/527
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 30
the CCLK and SCLK timing specifications in
Table
not select core/peripheral clocks in excess of the processor's
speed grade.
Table 30. Clock and Reset Timing
1
2
Parameter
Timing Requirements
t
t
t
t
Switching Characteristic
t
Applies to bypass mode and non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
CKIN
CKINL
CKINH
WRST
BUFDLAY
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
17, combinations of CLKIN and clock multipliers must
and
Figure 9
CLKBUF
CLKIN
RESET
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
CLKIN to CLKBUF Delay
describe clock and reset operations. Per
t
CKINL
t
1
CKIN
1
t
CKINH
Table 12
Rev. PrG | Page 38 of 80 | February 2009
2
to
Figure 9. Clock and Reset Timing
t
WRST
t
BUFDLAY
11
20.0
10.0
10.0
Min
t
CKIN
Preliminary Technical Data
t
BUFDLAY
100.0
Max
10
ns
Unit
ns
ns
ns
ns