ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 60

• Manufacturer Part Number: ADZS-BF527-EZLITE
• Description: BOARD EVAL ADSP-BF527
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF527-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Evaluation Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Silicon Core Number: ADSP-BF527
• Silicon Family Name: Blackfin
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF522/523/524/525/526/527
10/100 Ethernet MAC Controller Timing
Table 50
describe the 10/100 Ethernet MAC Controller operations.
Table 50. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Table 51. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Table 52. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
1
Table 53. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
1
Parameter
t
t
t
t
Parameter
t
t
t
t
Parameter
t
t
t
t
Parameter
t
t
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
MII outputs synchronous to ETxCLK are ETxD3–0.
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
ERXCLKF
ERXCLKW
ERXCLKIS
ERXCLKIH
ETXCLKF
ETXCLKW
ETXCLKOV
ETXCLKOH
EREFCLKF
EREFCLKW
EREFCLKIS
EREFCLKIH
EREFCLKOV
EREFCLKOH
through
1
1
1
1
Table 55
ERxCLK Frequency (f
ERxCLK Width (t
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
ETxCLK Frequency (f
ETxCLK Width (t
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out
Hold)
REF_CLK Frequency (f
EREF_CLK Width (t
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In
Hold)
RMII REF_CLK Rising Edge
to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge
to Tx Output Invalid (Data Out Hold)
and
Figure 35
ETxCLK
ERxCLK
EREFCLK
SCLK
SCLK
= ETxCLK Period)
= ERxCLK Period)
SCLK
through
= SCLK Frequency)
= SCLK Frequency)
= EREFCLK Period)
= SCLK Frequency)
Rev. PrG | Page 60 of 80 | February 2009
Figure 40
t
t
t
EREFCLK
Min
ERxCLK
ETxCLK
ADSP-BF522/524/526
2
V
None
None
None
1.8 V
DDEXT
Min
Min
Min
7.5
7.5
0
4
2
x 40% t
x 40%
V
V
V
x 40% t
Max
DDEXT
DDEXT
DDEXT
8.1
=
= 1.8 V
= 1.8 V
= 1.8 V
2 x f
t
EREFCLK
Min
ERxCLK
ETxCLK
f
f
2.5/3.3 V
2
25 + 1%
SCLK
25 + 1%
SCLK
50 + 1%
V
DDEXT
Max
Max
Max
SCLK
Preliminary Technical Data
20
+ 1%
+ 1%
x 60% t
x 60%
x 60% t
+ 1%
Max
8.1
=
t
Min
EREFCLK
ERxCLK
ETxCLK
ADSP-BF523/525/527
2
V
None
None
None
1.8 V
DDEXT
Min
Min
Min
V
V
V
7.5
7.5
0
4
2
DDEXT
DDEXT
DDEXT
x 35%
x 35% t
x 35% t
Max
7.5
=
= 2.5/3.3 V
= 2.5/3.3 V
= 2.5/3.3 V
2 x f
t
Min
EREFCLK
ERxCLK
ETxCLK
f
f
2.5/3.3 V
2
25 + 1%
25 + 1%
50 + 1%
V
SCLK
SCLK
DDEXT
Max
Max
Max
SCLK
20
+ 1%
+ 1%
x 65% ns
x 65% ns
x 65% ns
+ 1%
Max Unit
7.5
=
Unit
MHz
ns
ns
Unit
MHz
ns
ns
Unit
MHz
ns
ns
ns
ns