ADZS-BF527-EZLITE Analog Devices Inc, ADZS-BF527-EZLITE Datasheet - Page 22
![BOARD EVAL ADSP-BF527](/photos/9/22/92228/analog_devices_adzs-bf527-ezlite_sml.jpg)
ADZS-BF527-EZLITE
Manufacturer Part Number
ADZS-BF527-EZLITE
Description
BOARD EVAL ADSP-BF527
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Datasheet
1.ADZS-BF527-EZLITE.pdf
(80 pages)
Specifications of ADZS-BF527-EZLITE
Featured Product
Blackfin® BF50x Series Processors
Contents
Evaluation Board
Silicon Manufacturer
Analog Devices
Core Architecture
Blackfin
Features
USB-based, PC-hosted Tool Set
Silicon Core Number
ADSP-BF527
Silicon Family Name
Blackfin
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADSP-BF527
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
ADSP-BF522/523/524/525/526/527
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF522/524/526 and
ADSP-BF523/525/527 processors are listed in
to maintain maximum function and reduce package size and
ball count, some balls have dual, multiplexed functions. In cases
where ball function is reconfigurable, the default state is shown
in plain text, while the alternate function is shown in italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate.
All I/O pins have their input buffers disabled with the exception
of the pins that need pull-ups or pull-downs, as noted in
Table
Table 10. Signal Descriptions
Signal Name
EBIU
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
AMS3–0
ARDY
AOE
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
10.
Table
Type Function
O
I/O
O
O
I
O
O
O
O
O
O
O
O
O
O
Rev. PrG | Page 22 of 80 | February 2009
10. In order
Address Bus
Hardware Ready Control
Output Enable
SDRAM Clock Enable
SDRAM Clock Output
SDRAM A10 Signal
Data Bus
Byte Enables/Data Mask
Bank Select
Read Enable
Write Enable
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Write Enable
SDRAM Bank Select
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D.
The termination resistors should be placed near the processor to
reduce transients and improve signal integrity. The resistance
value, typically 33
average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
Preliminary Technical Data
or 47 , should be chosen to match the
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
B
A
A
1